From 20d9591cb6688a86316ef6990c1d1f4b71fded31 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 17 Aug 2021 17:36:31 +0800 Subject: [PATCH] clk: rockchip: optimize static memory consume Before: text data bss dec hex filename 5661 24 16 5701 1645 clk.o 10990 0 36 11026 2b12 clk-pll.o 2288 0 0 2288 8f0 clk-cpu.o 1856 0 0 1856 740 clk-half-divider.o 607 0 0 607 25f clk-inverter.o 872 0 0 872 368 clk-mmc-phase.o 580 0 0 580 244 clk-muxgrf.o 1524 0 12 1536 600 clk-ddr.o 1322 0 0 1322 52a clk-dclk-divider.o 2368 160 0 2528 9e0 clk-pvtm.o After: text data bss dec hex filename 5461 24 16 5501 157d clk.o 4864 0 36 4900 1324 clk-pll.o 2164 0 0 2164 874 clk-cpu.o 1856 0 0 1856 740 clk-half-divider.o 872 0 0 872 368 clk-mmc-phase.o 580 0 0 580 244 clk-muxgrf.o 908 0 8 916 394 clk-ddr.o 660 0 0 660 294 softrst.o Signed-off-by: Elaine Zhang Change-Id: I469229b9566af1cab6cc3a6bb9f4f8e308e0eded --- drivers/clk/rockchip/Kconfig | 55 ++++++++++++++++++++++++++++++++++ drivers/clk/rockchip/Makefile | 6 ++-- drivers/clk/rockchip/clk-cpu.c | 11 ++++--- drivers/clk/rockchip/clk-ddr.c | 4 +++ drivers/clk/rockchip/clk-pll.c | 27 +++++++++++++---- drivers/clk/rockchip/clk.c | 4 +++ 6 files changed, 94 insertions(+), 13 deletions(-) diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index 5764624a103b..a73fea168424 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -148,6 +148,61 @@ config ROCKCHIP_CLK_LINK help Say y here to enable clock link for Rockchip. +config ROCKCHIP_CLK_BOOST + bool "Rockchip Clk Boost" + default y if CPU_PX30 + help + Say y here to enable clk boost. + +config ROCKCHIP_CLK_INV + bool "Rockchip Clk Inverter" + default y if !CPU_RV1126 && !CPU_RV1106 + help + Say y here to enable clk Inverter. + +config ROCKCHIP_CLK_PVTM + bool "Rockchip Clk Pvtm" + default y if !CPU_RV1126 && !CPU_RV1106 + help + Say y here to enable clk pvtm. + +config ROCKCHIP_DCLK_DIV + bool "Rockchip Dclk Divider" + default y if !CPU_RV1126 && !CPU_RV1106 + help + Say y here to enable dclk divider. + +config ROCKCHIP_DDRCLK_SCPI + bool "Rockchip DDR Clk SCPI" + default y if RK3368_SCPI_PROTOCOL + help + Say y here to enable ddr clk scpi. + +config ROCKCHIP_DDRCLK_SIP + bool "Rockchip DDR Clk SIP" + default y if CPU_RK3399 + help + Say y here to enable ddr clk sip. + +config ROCKCHIP_PLL_RK3066 + bool "Rockchip PLL Type RK3066" + default y if CPU_RK30XX || CPU_RK3188 || \ + CPU_RK3288 || CPU_RK3368 + help + Say y here to enable pll type is rk3066. + +config ROCKCHIP_PLL_RK3399 + bool "Rockchip PLL Type RK3399" + default y if CPU_RK3399 || CPU_RV1108 + help + Say y here to enable pll type is rk3399. + +config ROCKCHIP_PLL_RK3588 + bool "Rockchip PLL Type RK3588" + default y if CPU_RK3588 + help + Say y here to enable pll type is rk3588. + source "drivers/clk/rockchip/regmap/Kconfig" endif diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index a5c10fb1f10a..e45fa0a0ba0d 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -10,12 +10,12 @@ clk-rockchip-y += clk.o clk-rockchip-y += clk-pll.o clk-rockchip-y += clk-cpu.o clk-rockchip-y += clk-half-divider.o -clk-rockchip-y += clk-inverter.o clk-rockchip-y += clk-mmc-phase.o clk-rockchip-y += clk-muxgrf.o clk-rockchip-y += clk-ddr.o -clk-rockchip-y += clk-dclk-divider.o -clk-rockchip-y += clk-pvtm.o +clk-rockchip-$(CONFIG_ROCKCHIP_CLK_INV) += clk-inverter.o +clk-rockchip-$(CONFIG_ROCKCHIP_CLK_PVTM) += clk-pvtm.o +clk-rockchip-$(CONFIG_ROCKCHIP_DCLK_DIV) += clk-dclk-divider.o clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o obj-$(CONFIG_ROCKCHIP_CLK_LINK) += clk-link.o diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 3293174a62c6..6bcb07931fca 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -171,7 +171,8 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, return -EINVAL; } - rockchip_boost_enable_recovery_sw_low(cpuclk->pll_hw); + if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST)) + rockchip_boost_enable_recovery_sw_low(cpuclk->pll_hw); alt_prate = clk_get_rate(cpuclk->alt_parent); @@ -209,7 +210,8 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, } } - rockchip_boost_add_core_div(cpuclk->pll_hw, alt_prate); + if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST)) + rockchip_boost_add_core_div(cpuclk->pll_hw, alt_prate); rockchip_cpuclk_set_pre_muxs(cpuclk, rate); @@ -279,7 +281,8 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk, if (ndata->old_rate > ndata->new_rate) rockchip_cpuclk_set_dividers(cpuclk, rate); - rockchip_boost_disable_recovery_sw(cpuclk->pll_hw); + if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST)) + rockchip_boost_disable_recovery_sw(cpuclk->pll_hw); spin_unlock_irqrestore(cpuclk->lock, flags); return 0; @@ -354,7 +357,7 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, cpuclk->reg_data = reg_data; cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb; cpuclk->hw.init = &init; - if (reg_data->pll_name) { + if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST) && reg_data->pll_name) { pll_clk = clk_get_parent(parent); if (!pll_clk) { pr_err("%s: could not lookup pll clock: (%s)\n", diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c index 3c8bcbee2048..31cef4cd9240 100644 --- a/drivers/clk/rockchip/clk-ddr.c +++ b/drivers/clk/rockchip/clk-ddr.c @@ -259,12 +259,16 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, init.flags |= CLK_SET_RATE_NO_REPARENT; switch (ddr_flag) { +#ifdef CONFIG_ROCKCHIP_DDRCLK_SIP case ROCKCHIP_DDRCLK_SIP: init.ops = &rockchip_ddrclk_sip_ops; break; +#endif +#ifdef CONFIG_ROCKCHIP_DDRCLK_SCPI case ROCKCHIP_DDRCLK_SCPI: init.ops = &rockchip_ddrclk_scpi_ops; break; +#endif case ROCKCHIP_DDRCLK_SIP_V2: init.ops = &rockchip_ddrclk_sip_ops_v2; break; diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 92fe99b4bdf4..99eece683909 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -47,12 +47,14 @@ struct rockchip_clk_pll { struct rockchip_clk_provider *ctx; +#ifdef CONFIG_ROCKCHIP_CLK_BOOST bool boost_enabled; u32 boost_backup_pll_usage; unsigned long boost_backup_pll_rate; unsigned long boost_low_rate; unsigned long boost_high_rate; struct regmap *boost; +#endif #ifdef CONFIG_DEBUG_FS struct hlist_node debug_node; #endif @@ -62,7 +64,15 @@ struct rockchip_clk_pll { #define to_rockchip_clk_pll_nb(nb) \ container_of(nb, struct rockchip_clk_pll, clk_nb) +#ifdef CONFIG_ROCKCHIP_CLK_BOOST static void rockchip_boost_disable_low(struct rockchip_clk_pll *pll); +#ifdef CONFIG_DEBUG_FS +static HLIST_HEAD(clk_boost_list); +static DEFINE_MUTEX(clk_boost_lock); +#endif +#else +static inline void rockchip_boost_disable_low(struct rockchip_clk_pll *pll) {} +#endif #define MHZ (1000UL * 1000UL) #define KHZ (1000UL) @@ -86,10 +96,6 @@ static void rockchip_boost_disable_low(struct rockchip_clk_pll *pll); #define MAX_FOUTVCO_FREQ (2000 * MHZ) static struct rockchip_pll_rate_table auto_table; -#ifdef CONFIG_DEBUG_FS -static HLIST_HEAD(clk_boost_list); -static DEFINE_MUTEX(clk_boost_lock); -#endif int rockchip_pll_clk_adaptive_scaling(struct clk *clk, int sel) { @@ -477,7 +483,7 @@ static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll) return ret; } -static unsigned long +static unsigned long __maybe_unused rockchip_rk3036_pll_con_to_rate(struct rockchip_clk_pll *pll, u32 con0, u32 con1) { @@ -599,7 +605,8 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); - rockchip_boost_disable_low(pll); + if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST)) + rockchip_boost_disable_low(pll); /* wait for the pll to lock */ ret = rockchip_rk3036_pll_wait_lock(pll); @@ -1656,18 +1663,23 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, else init.ops = &rockchip_rk3036_pll_clk_ops; break; +#ifdef CONFIG_ROCKCHIP_PLL_RK3066 case pll_rk3066: if (!pll->rate_table || IS_ERR(ctx->grf)) init.ops = &rockchip_rk3066_pll_clk_norate_ops; else init.ops = &rockchip_rk3066_pll_clk_ops; break; +#endif +#ifdef CONFIG_ROCKCHIP_PLL_RK3399 case pll_rk3399: if (!pll->rate_table) init.ops = &rockchip_rk3399_pll_clk_norate_ops; else init.ops = &rockchip_rk3399_pll_clk_ops; break; +#endif +#ifdef CONFIG_ROCKCHIP_PLL_RK3588 case pll_rk3588: case pll_rk3588_core: if (!pll->rate_table) @@ -1676,6 +1688,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, init.ops = &rockchip_rk3588_pll_clk_ops; init.flags = flags; break; +#endif default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, name); @@ -1707,6 +1720,7 @@ err_mux: return mux_clk; } +#ifdef CONFIG_ROCKCHIP_CLK_BOOST static unsigned long rockchip_pll_con_to_rate(struct rockchip_clk_pll *pll, u32 con0, u32 con1) { @@ -2019,3 +2033,4 @@ static int __init boost_debug_init(void) late_initcall(boost_debug_init); #endif /* MODULE */ #endif /* CONFIG_DEBUG_FS */ +#endif /* CONFIG_ROCKCHIP_CLK_BOOST */ diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 6c8e47067032..b2d104fc15f6 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -654,11 +654,13 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, ); break; case branch_inverter: +#ifdef CONFIG_ROCKCHIP_CLK_INV clk = rockchip_clk_register_inverter( list->name, list->parent_names, list->num_parents, ctx->reg_base + list->muxdiv_offset, list->div_shift, list->div_flags, &ctx->lock); +#endif break; case branch_factor: clk = rockchip_clk_register_factor_branch( @@ -678,6 +680,7 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, ctx->reg_base); break; case branch_dclk_divider: +#ifdef CONFIG_ROCKCHIP_DCLK_DIV clk = rockchip_clk_register_dclk_branch(list->name, list->parent_names, list->num_parents, ctx->reg_base, list->muxdiv_offset, list->mux_shift, @@ -686,6 +689,7 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, list->div_flags, list->div_table, list->gate_offset, list->gate_shift, list->gate_flags, flags, list->max_prate, &ctx->lock); +#endif break; }