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Merge branch 'develop-4.19-px30s'

Browse Source 
Change-Id: I5c3e5e4d477cb439bee3dde09978e4380799ffe7
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This commit is contained in:
Tao Huang
2022-01-20 14:35:41 +08:00
parent b5f03114e3 d78fd6663e
commit 218dfa33d2
40 changed files with 2115 additions and 1009 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/rockchip/px30-ad-d6-anx6345.dts
View File

@@ -235,7 +235,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -250,7 +250,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;

4
arch/arm64/boot/dts/rockchip/px30-ad-r35-mb.dtsi
View File

@@ -187,7 +187,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;
@@ -202,7 +202,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;

4
arch/arm64/boot/dts/rockchip/px30-evb-ddr3-lvds-v10.dts
View File

@@ -258,7 +258,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;
@@ -272,7 +272,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;

309
arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-avb.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017-2019 Fuzhou Rockchip Electronics Co., Ltd
* Copyright (c) 2017-2021 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
@@ -9,6 +9,28 @@
/ {
model = "Rockchip PX30 evb ddr3 board";
compatible = "rockchip,px30-evb-ddr3-v10-avb", "rockchip,px30";
rk_headset: rk-headset {
compatible = "rockchip_headset";
headset_gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hp_det>;
io-channels = <&saradc 1>;
};
wireless-bluetooth {
compatible = "bluetooth-platdata";
clocks = <&rk809 1>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default","rts_gpio";
pinctrl-0 = <&uart1_rts>;
pinctrl-1 = <&uart1_rts_gpio>;
BT,reset_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
BT,wake_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&chosen {
@@ -19,16 +41,16 @@
status = "okay";
panel@0 {
compatible = "sitronix,st7703", "simple-panel-dsi";
compatible = "simple-panel-dsi";
reg = <0>;
power-supply = <&vcc3v3_lcd>;
backlight = <&backlight>;
prepare-delay-ms = <2>;
reset-delay-ms = <1>;
init-delay-ms = <20>;
enable-delay-ms = <120>;
disable-delay-ms = <50>;
unprepare-delay-ms = <20>;
prepare-delay-ms = <0>;
reset-delay-ms = <0>;
init-delay-ms = <80>;
enable-delay-ms = <0>;
disable-delay-ms = <10>;
unprepare-delay-ms = <60>;
width-mm = <68>;
height-mm = <121>;
@@ -39,46 +61,212 @@
dsi,lanes = <4>;
panel-init-sequence = [
05 fa 01 11
39 00 04 b9 f1 12 83
39 00 1c ba 33 81 05 f9 0e 0e 00 00 00
00 00 00 00 00 44 25 00 91 0a
00 00 02 4f 01 00 00 37
15 00 02 b8 25
39 00 04 bf 02 11 00
39 00 0b b3 0c 10 0a 50 03 ff 00 00 00
00
39 00 0a c0 73 73 50 50 00 00 08 70 00
15 00 02 bc 46
15 00 02 cc 0b
15 00 02 b4 80
39 00 04 b2 c8 12 30
39 00 0f e3 07 07 0b 0b 03 0b 00 00 00
00 ff 00 c0 10
39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67
77 33 33
39 00 07 c6 00 00 ff ff 01 ff
39 00 03 b5 09 09
39 00 03 b6 87 95
39 00 40 e9 c2 10 05 05 10 05 a0 12 31
23 3f 81 0a a0 37 18 00 80 01
00 00 00 00 80 01 00 00 00 48
f8 86 42 08 88 88 80 88 88 88
58 f8 87 53 18 88 88 81 88 88
88 00 00 00 01 00 00 00 00 00
00 00 00 00
39 00 3e ea 00 1a 00 00 00 00 02 00 00
00 00 00 1f 88 81 35 78 88 88
85 88 88 88 0f 88 80 24 68 88
88 84 88 88 88 23 10 00 00 1c
00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 30 05 a0 00 00
00 00
39 00 23 e0 00 06 08 2a 31 3f 38 36 07
0c 0d 11 13 12 13 11 18 00 06
08 2a 31 3f 38 36 07 0c 0d 11
13 12 13 11 18
05 32 01 29
39 00 04 ff 98 81 03
15 00 02 01 00
15 00 02 02 00
15 00 02 03 53
15 00 02 04 53
15 00 02 05 13
15 00 02 06 04
15 00 02 07 02
15 00 02 08 02
15 00 02 09 00
15 00 02 0a 00
15 00 02 0b 00
15 00 02 0c 00
15 00 02 0d 00
15 00 02 0e 00
15 00 02 0f 00
15 00 02 10 00
15 00 02 11 00
15 00 02 12 00
15 00 02 13 00
15 00 02 14 00
15 00 02 15 08
15 00 02 16 10
15 00 02 17 00
15 00 02 18 08
15 00 02 19 00
15 00 02 1a 00
15 00 02 1b 00
15 00 02 1c 00
15 00 02 1d 00
15 00 02 1e c0
15 00 02 1f 80
15 00 02 20 02
15 00 02 21 09
15 00 02 22 00
15 00 02 23 00
15 00 02 24 00
15 00 02 25 00
15 00 02 26 00
15 00 02 27 00
15 00 02 28 55
15 00 02 29 03
15 00 02 2a 00
15 00 02 2b 00
15 00 02 2c 00
15 00 02 2d 00
15 00 02 2e 00
15 00 02 2f 00
15 00 02 30 00
15 00 02 31 00
15 00 02 32 00
15 00 02 33 00
15 00 02 34 04
15 00 02 35 05
15 00 02 36 05
15 00 02 37 00
15 00 02 38 3c
15 00 02 39 35
15 00 02 3a 00
15 00 02 3b 40
15 00 02 3c 00
15 00 02 3d 00
15 00 02 3e 00
15 00 02 3f 00
15 00 02 40 00
15 00 02 41 88
15 00 02 42 00
15 00 02 43 00
15 00 02 44 1f
15 00 02 50 01
15 00 02 51 23
15 00 02 52 45
15 00 02 53 67
15 00 02 54 89
15 00 02 55 ab
15 00 02 56 01
15 00 02 57 23
15 00 02 58 45
15 00 02 59 67
15 00 02 5a 89
15 00 02 5b ab
15 00 02 5c cd
15 00 02 5d ef
15 00 02 5e 03
15 00 02 5f 14
15 00 02 60 15
15 00 02 61 0c
15 00 02 62 0d
15 00 02 63 0e
15 00 02 64 0f
15 00 02 65 10
15 00 02 66 11
15 00 02 67 08
15 00 02 68 02
15 00 02 69 0a
15 00 02 6a 02
15 00 02 6b 02
15 00 02 6c 02
15 00 02 6d 02
15 00 02 6e 02
15 00 02 6f 02
15 00 02 70 02
15 00 02 71 02
15 00 02 72 06
15 00 02 73 02
15 00 02 74 02
15 00 02 75 14
15 00 02 76 15
15 00 02 77 0f
15 00 02 78 0e
15 00 02 79 0d
15 00 02 7a 0c
15 00 02 7b 11
15 00 02 7c 10
15 00 02 7d 06
15 00 02 7e 02
15 00 02 7f 0a
15 00 02 80 02
15 00 02 81 02
15 00 02 82 02
15 00 02 83 02
15 00 02 84 02
15 00 02 85 02
15 00 02 86 02
15 00 02 87 02
15 00 02 88 08
15 00 02 89 02
15 00 02 8a 02
39 00 04 ff 98 81 04
15 00 02 00 80
15 00 02 70 00
15 00 02 71 00
15 00 02 66 fe
15 00 02 82 15
15 00 02 84 15
15 00 02 85 15
15 00 02 3a 24
15 00 02 32 ac
15 00 02 8c 80
15 00 02 3c f5
15 00 02 88 33
39 00 04 ff 98 81 01
15 00 02 22 0a
15 00 02 31 00
15 00 02 53 78
15 00 02 50 5b
15 00 02 51 5b
15 00 02 60 20
15 00 02 61 00
15 00 02 62 0d
15 00 02 63 00
15 00 02 a0 00
15 00 02 a1 10
15 00 02 a2 1c
15 00 02 a3 13
15 00 02 a4 15
15 00 02 a5 26
15 00 02 a6 1a
15 00 02 a7 1d
15 00 02 a8 67
15 00 02 a9 1c
15 00 02 aa 29
15 00 02 ab 5b
15 00 02 ac 26
15 00 02 ad 28
15 00 02 ae 5c
15 00 02 af 30
15 00 02 b0 31
15 00 02 b1 2e
15 00 02 b2 32
15 00 02 b3 00
15 00 02 c0 00
15 00 02 c1 10
15 00 02 c2 1c
15 00 02 c3 13
15 00 02 c4 15
15 00 02 c5 26
15 00 02 c6 1a
15 00 02 c7 1d
15 00 02 c8 67
15 00 02 c9 1c
15 00 02 ca 29
15 00 02 cb 5b
15 00 02 cc 26
15 00 02 cd 28
15 00 02 ce 5c
15 00 02 cf 30
15 00 02 d0 31
15 00 02 d1 2e
15 00 02 d2 32
15 00 02 d3 00
39 00 04 ff 98 81 00
05 00 01 11
05 01 01 29
];
panel-exit-sequence = [
@@ -87,9 +275,9 @@
];
display-timings {
native-mode = <&timing0>;
native-mode = <&timing1>;
timing0: timing0 {
timing1: timing1 {
clock-frequency = <64000000>;
hactive = <720>;
vactive = <1280>;
@@ -107,3 +295,24 @@
};
};
};
&gmac {
phy-supply = <&vcc_phy>;
clock_in_out = "input";
assigned-clocks = <&cru SCLK_GMAC>;
assigned-clock-parents = <&gmac_clkin>;
pinctrl-names = "default";
pinctrl-0 = <&rmii_pins &mac_refclk>;
snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 50000 50000>;
status = "okay";
};
&pinctrl {
headphone {
hp_det: hp-det {
rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};

280
arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-linux.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
* Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
@@ -178,8 +178,8 @@
pinctrl-names = "default","rts_gpio";
pinctrl-0 = <&uart1_rts>;
pinctrl-1 = <&uart1_rts_gpio>;
BT,reset_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
BT,wake_gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>;
BT,reset_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
BT,wake_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
status = "okay";
};
@@ -193,16 +193,16 @@
status = "okay";
panel@0 {
compatible = "sitronix,st7703", "simple-panel-dsi";
compatible = "simple-panel-dsi";
reg = <0>;
power-supply = <&vcc3v3_lcd>;
backlight = <&backlight>;
prepare-delay-ms = <2>;
reset-delay-ms = <1>;
init-delay-ms = <20>;
enable-delay-ms = <120>;
disable-delay-ms = <50>;
unprepare-delay-ms = <20>;
prepare-delay-ms = <0>;
reset-delay-ms = <0>;
init-delay-ms = <80>;
enable-delay-ms = <0>;
disable-delay-ms = <10>;
unprepare-delay-ms = <60>;
width-mm = <68>;
height-mm = <121>;
@@ -213,46 +213,212 @@
dsi,lanes = <4>;
panel-init-sequence = [
05 fa 01 11
39 00 04 b9 f1 12 83
39 00 1c ba 33 81 05 f9 0e 0e 00 00 00
00 00 00 00 00 44 25 00 91 0a
00 00 02 4f 01 00 00 37
15 00 02 b8 25
39 00 04 bf 02 11 00
39 00 0b b3 0c 10 0a 50 03 ff 00 00 00
00
39 00 0a c0 73 73 50 50 00 00 08 70 00
15 00 02 bc 46
15 00 02 cc 0b
15 00 02 b4 80
39 00 04 b2 c8 12 30
39 00 0f e3 07 07 0b 0b 03 0b 00 00 00
00 ff 00 c0 10
39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67
77 33 33
39 00 07 c6 00 00 ff ff 01 ff
39 00 03 b5 09 09
39 00 03 b6 87 95
39 00 40 e9 c2 10 05 05 10 05 a0 12 31
23 3f 81 0a a0 37 18 00 80 01
00 00 00 00 80 01 00 00 00 48
f8 86 42 08 88 88 80 88 88 88
58 f8 87 53 18 88 88 81 88 88
88 00 00 00 01 00 00 00 00 00
00 00 00 00
39 00 3e ea 00 1a 00 00 00 00 02 00 00
00 00 00 1f 88 81 35 78 88 88
85 88 88 88 0f 88 80 24 68 88
88 84 88 88 88 23 10 00 00 1c
00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 30 05 a0 00 00
00 00
39 00 23 e0 00 06 08 2a 31 3f 38 36 07
0c 0d 11 13 12 13 11 18 00 06
08 2a 31 3f 38 36 07 0c 0d 11
13 12 13 11 18
05 32 01 29
39 00 04 ff 98 81 03
15 00 02 01 00
15 00 02 02 00
15 00 02 03 53
15 00 02 04 53
15 00 02 05 13
15 00 02 06 04
15 00 02 07 02
15 00 02 08 02
15 00 02 09 00
15 00 02 0a 00
15 00 02 0b 00
15 00 02 0c 00
15 00 02 0d 00
15 00 02 0e 00
15 00 02 0f 00
15 00 02 10 00
15 00 02 11 00
15 00 02 12 00
15 00 02 13 00
15 00 02 14 00
15 00 02 15 08
15 00 02 16 10
15 00 02 17 00
15 00 02 18 08
15 00 02 19 00
15 00 02 1a 00
15 00 02 1b 00
15 00 02 1c 00
15 00 02 1d 00
15 00 02 1e c0
15 00 02 1f 80
15 00 02 20 02
15 00 02 21 09
15 00 02 22 00
15 00 02 23 00
15 00 02 24 00
15 00 02 25 00
15 00 02 26 00
15 00 02 27 00
15 00 02 28 55
15 00 02 29 03
15 00 02 2a 00
15 00 02 2b 00
15 00 02 2c 00
15 00 02 2d 00
15 00 02 2e 00
15 00 02 2f 00
15 00 02 30 00
15 00 02 31 00
15 00 02 32 00
15 00 02 33 00
15 00 02 34 04
15 00 02 35 05
15 00 02 36 05
15 00 02 37 00
15 00 02 38 3c
15 00 02 39 35
15 00 02 3a 00
15 00 02 3b 40
15 00 02 3c 00
15 00 02 3d 00
15 00 02 3e 00
15 00 02 3f 00
15 00 02 40 00
15 00 02 41 88
15 00 02 42 00
15 00 02 43 00
15 00 02 44 1f
15 00 02 50 01
15 00 02 51 23
15 00 02 52 45
15 00 02 53 67
15 00 02 54 89
15 00 02 55 ab
15 00 02 56 01
15 00 02 57 23
15 00 02 58 45
15 00 02 59 67
15 00 02 5a 89
15 00 02 5b ab
15 00 02 5c cd
15 00 02 5d ef
15 00 02 5e 03
15 00 02 5f 14
15 00 02 60 15
15 00 02 61 0c
15 00 02 62 0d
15 00 02 63 0e
15 00 02 64 0f
15 00 02 65 10
15 00 02 66 11
15 00 02 67 08
15 00 02 68 02
15 00 02 69 0a
15 00 02 6a 02
15 00 02 6b 02
15 00 02 6c 02
15 00 02 6d 02
15 00 02 6e 02
15 00 02 6f 02
15 00 02 70 02
15 00 02 71 02
15 00 02 72 06
15 00 02 73 02
15 00 02 74 02
15 00 02 75 14
15 00 02 76 15
15 00 02 77 0f
15 00 02 78 0e
15 00 02 79 0d
15 00 02 7a 0c
15 00 02 7b 11
15 00 02 7c 10
15 00 02 7d 06
15 00 02 7e 02
15 00 02 7f 0a
15 00 02 80 02
15 00 02 81 02
15 00 02 82 02
15 00 02 83 02
15 00 02 84 02
15 00 02 85 02
15 00 02 86 02
15 00 02 87 02
15 00 02 88 08
15 00 02 89 02
15 00 02 8a 02
39 00 04 ff 98 81 04
15 00 02 00 80
15 00 02 70 00
15 00 02 71 00
15 00 02 66 fe
15 00 02 82 15
15 00 02 84 15
15 00 02 85 15
15 00 02 3a 24
15 00 02 32 ac
15 00 02 8c 80
15 00 02 3c f5
15 00 02 88 33
39 00 04 ff 98 81 01
15 00 02 22 0a
15 00 02 31 00
15 00 02 53 78
15 00 02 50 5b
15 00 02 51 5b
15 00 02 60 20
15 00 02 61 00
15 00 02 62 0d
15 00 02 63 00
15 00 02 a0 00
15 00 02 a1 10
15 00 02 a2 1c
15 00 02 a3 13
15 00 02 a4 15
15 00 02 a5 26
15 00 02 a6 1a
15 00 02 a7 1d
15 00 02 a8 67
15 00 02 a9 1c
15 00 02 aa 29
15 00 02 ab 5b
15 00 02 ac 26
15 00 02 ad 28
15 00 02 ae 5c
15 00 02 af 30
15 00 02 b0 31
15 00 02 b1 2e
15 00 02 b2 32
15 00 02 b3 00
15 00 02 c0 00
15 00 02 c1 10
15 00 02 c2 1c
15 00 02 c3 13
15 00 02 c4 15
15 00 02 c5 26
15 00 02 c6 1a
15 00 02 c7 1d
15 00 02 c8 67
15 00 02 c9 1c
15 00 02 ca 29
15 00 02 cb 5b
15 00 02 cc 26
15 00 02 cd 28
15 00 02 ce 5c
15 00 02 cf 30
15 00 02 d0 31
15 00 02 d1 2e
15 00 02 d2 32
15 00 02 d3 00
39 00 04 ff 98 81 00
05 00 01 11
05 01 01 29
];
panel-exit-sequence = [
@@ -350,7 +516,11 @@
&gmac {
phy-supply = <&vcc_phy>;
clock_in_out = "output";
clock_in_out = "input";
assigned-clocks = <&cru SCLK_GMAC>;
assigned-clock-parents = <&gmac_clkin>;
pinctrl-names = "default";
pinctrl-0 = <&rmii_pins &mac_refclk>;
snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 50000 50000>;
@@ -427,7 +597,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -441,7 +611,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -487,7 +657,7 @@
};
};
vcc1v8_soc: LDO_REG2 {
vccio_sdio: vcc1v8_soc: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
@@ -702,7 +872,7 @@
&io_domains {
status = "okay";
vccio1-supply = <&vcc_3v0>;
vccio1-supply = <&vccio_sdio>;
vccio2-supply = <&vccio_sd>;
vccio3-supply = <&vcc_3v0>;
vccio4-supply = <&vcc3v0_pmu>;

4
arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-robot-linux.dts
View File

@@ -203,7 +203,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -217,7 +217,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;

4
arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-robot-no-gpu-linux.dts
View File

@@ -203,7 +203,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -217,7 +217,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;

13
arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dts
View File

@@ -125,3 +125,16 @@
};
};
};
&gmac {
phy-supply = <&vcc_phy>;
clock_in_out = "input";
assigned-clocks = <&cru SCLK_GMAC>;
assigned-clock-parents = <&gmac_clkin>;
pinctrl-names = "default";
pinctrl-0 = <&rmii_pins &mac_refclk>;
snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 50000 50000>;
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dtsi
View File

@@ -311,7 +311,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -325,7 +325,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;

979
arch/arm64/boot/dts/rockchip/px30-evb-ddr4-v10.dts
View File

File diff suppressed because it is too large Load Diff

4
arch/arm64/boot/dts/rockchip/px30-z7-a0-rk618-dsi.dts
View File

@@ -332,7 +332,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -347,7 +347,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;

141
arch/arm64/boot/dts/rockchip/px30.dtsi
View File

@@ -16,6 +16,7 @@
#include <dt-bindings/suspend/rockchip-px30.h>
#include <dt-bindings/thermal/thermal.h>
#include "px30-dram-default-timing.dtsi"
#include "px30s-dram-default-timing.dtsi"
/ {
compatible = "rockchip,px30";
@@ -230,6 +231,58 @@
};
};
px30s_cpu0_opp_table: px30s-cpu0-opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <850000 850000 1150000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <850000 850000 1150000>;
clock-latency-ns = <40000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <850000 850000 1150000>;
clock-latency-ns = <40000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <900000 900000 1150000>;
clock-latency-ns = <40000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <975000 975000 1150000>;
clock-latency-ns = <40000>;
};
opp-1248000000 {
opp-hz = /bits/ 64 <1248000000>;
opp-microvolt = <1000000 1000000 1150000>;
clock-latency-ns = <40000>;
};
opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
opp-microvolt = <1025000 1025000 1150000>;
clock-latency-ns = <40000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1075000 1075000 1150000>;
clock-latency-ns = <40000>;
};
opp-1512000000 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <1150000 1150000 1150000>;
clock-latency-ns = <40000>;
};
};
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
@@ -279,6 +332,24 @@
compatible = "linaro,optee-tz";
method = "smc";
};
scmi: scmi {
compatible = "arm,scmi-smc";
shmem = <&scmi_shmem>;
arm,smc-id = <0x82000010>;
#address-cells = <1>;
#size-cells = <0>;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
};
sdei: sdei {
compatible = "arm,sdei-1.0";
method = "smc";
};
};
gmac_clkin: external-gmac-clock {
@@ -337,6 +408,11 @@
clock-output-names = "xin32k";
};
scmi_shmem: scmi-shmem@10f000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x0010f000 0x0 0x100>;
};
pmu: power-management@ff000000 {
compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
reg = <0x0 0xff000000 0x0 0x1000>;
@@ -1388,6 +1464,27 @@
};
};
px30s_gpu_opp_table: px30s-gpu-opp-table {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <1000000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1000000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1000000>;
};
opp-520000000 {
opp-hz = /bits/ 64 <520000000>;
opp-microvolt = <1000000>;
};
};
mpp_srv: mpp-srv {
compatible = "rockchip,mpp-service";
rockchip,taskqueue-count = <1>;
@@ -1841,7 +1938,7 @@
SYS_STATUS_VIDEO_1080P 450000
SYS_STATUS_BOOST 528000
SYS_STATUS_ISP 666000
SYS_STATUS_PERFORMANCE 666000
SYS_STATUS_PERFORMANCE 1056000
>;
auto-min-freq = <328000>;
auto-freq-en = <1>;
@@ -1857,6 +1954,20 @@
};
};
dmc_fsp: dmc-fsp {
compatible = "rockchip,px30s-dmc-fsp";
debug_print_level = <0>;
phy_de_skew_en = <1>;
ddr3_params = <&ddr3_params>;
ddr4_params = <&ddr4_params>;
lpddr2_params = <&lpddr2_params>;
lpddr3_params = <&lpddr3_params>;
lpddr4_params = <&lpddr4_params>;
ddr_timing = <&ddr_timing>;
status = "okay";
};
dmc_opp_table: dmc-opp-table {
compatible = "operating-points-v2";
@@ -1922,6 +2033,34 @@
};
};
px30s_dmc_opp_table: px30s-dmc-opp-table {
compatible = "operating-points-v2";
opp-328000000 {
opp-hz = /bits/ 64 <328000000>;
opp-microvolt = <1000000>;
};
opp-666000000 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <1000000>;
};
opp-786000000 {
opp-hz = /bits/ 64 <786000000>;
opp-microvolt = <1000000>;
};
opp-924000000 {
opp-hz = /bits/ 64 <924000000>;
opp-microvolt = <1000000>;
status = "disabled";
};
/* 1056M only for LP4 */
opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
opp-microvolt = <1000000>;
status = "disabled";
};
};
dmcdbg: dmcdbg {
compatible = "rockchip,px30-dmcdbg";
status = "okay";

379
arch/arm64/boot/dts/rockchip/px30s-dram-default-timing.dtsi Normal file
View File

@@ -0,0 +1,379 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
*/
#include <dt-bindings/clock/rockchip-ddr.h>
#include <dt-bindings/memory/px30-dram.h>
/ {
ddr3_params: ddr3-params {
/* version information */
version = <0x101>;
expanded_version = <IGNORE_THIS>;
reserved = <IGNORE_THIS>;
/* freq info, freq_0 is final frequency, unit: MHz */
freq_0 = <924>;
freq_1 = <328>;
freq_2 = <666>;
freq_3 = <786>;
freq_4 = <IGNORE_THIS>;
freq_5 = <IGNORE_THIS>;
/* power save setting */
pd_idle = <13>;
sr_idle = <93>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
pd_dis_freq = <1066>;
sr_dis_freq = <800>;
dram_dll_dis_freq = <300>;
phy_dll_dis_freq = <IGNORE_THIS>;
/* drv when odt on */
phy_dq_drv_odten = <33>;
phy_ca_drv_odten = <33>;
phy_clk_drv_odten = <33>;
dram_dq_drv_odten = <34>;
/* drv when odt off */
phy_dq_drv_odtoff = <33>;
phy_ca_drv_odtoff = <33>;
phy_clk_drv_odtoff = <33>;
dram_dq_drv_odtoff = <34>;
/* odt info */
dram_odt = <120>;
phy_odt = <133>;
phy_odt_puup_en = <1>;
phy_odt_pudn_en = <1>;
/* odt enable freq */
dram_dq_odt_en_freq = <333>;
phy_odt_en_freq = <333>;
/* slew rate when odt enable */
phy_dq_sr_odten = <0xf>;
phy_ca_sr_odten = <0x3>;
phy_clk_sr_odten = <0x3>;
/* slew rate when odt disable */
phy_dq_sr_odtoff = <0xf>;
phy_ca_sr_odtoff = <0x3>;
phy_clk_sr_odtoff = <0x3>;
/* ssmod setting*/
ssmod_downspread = <0>;
ssmod_div = <0>;
ssmod_spread = <0>;
/* 2T mode */
mode_2t = <IGNORE_THIS>;
/* speed bin */
speed_bin = <DDR3_DEFAULT>;
/* dram extended temperature support */
dram_ext_temp = <0>;
/* byte map */
byte_map = <((0x2 << 6) | (0x3 << 4) | (0x0 << 2) | (0x1 << 0))>;
/* dq map */
dq_map_cs0_dq_l = <0>;
dq_map_cs0_dq_h = <0>;
dq_map_cs1_dq_l = <0>;
dq_map_cs1_dq_h = <0>;
};
ddr4_params: ddr4-params {
/* version information */
version = <0x101>;
expanded_version = <IGNORE_THIS>;
reserved = <IGNORE_THIS>;
/* freq info, freq_0 is final frequency, unit: MHz */
freq_0 = <924>;
freq_1 = <328>;
freq_2 = <666>;
freq_3 = <786>;
freq_4 = <IGNORE_THIS>;
freq_5 = <IGNORE_THIS>;
/* power save setting */
pd_idle = <13>;
sr_idle = <93>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
pd_dis_freq = <1066>;
sr_dis_freq = <800>;
dram_dll_dis_freq = <500>;
phy_dll_dis_freq = <IGNORE_THIS>;
/* drv when odt on */
phy_dq_drv_odten = <33>;
phy_ca_drv_odten = <33>;
phy_clk_drv_odten = <33>;
dram_dq_drv_odten = <34>;
/* drv when odt off */
phy_dq_drv_odtoff = <33>;
phy_ca_drv_odtoff = <33>;
phy_clk_drv_odtoff = <33>;
dram_dq_drv_odtoff = <34>;
/* odt info */
dram_odt = <120>;
phy_odt = <121>;
phy_odt_puup_en = <1>;
phy_odt_pudn_en = <1>;
/* odt enable freq */
dram_dq_odt_en_freq = <500>;
phy_odt_en_freq = <500>;
/* slew rate when odt enable */
phy_dq_sr_odten = <0xe>;
phy_ca_sr_odten = <0x1>;
phy_clk_sr_odten = <0x1>;
/* slew rate when odt disable */
phy_dq_sr_odtoff = <0xe>;
phy_ca_sr_odtoff = <0x1>;
phy_clk_sr_odtoff = <0x1>;
/* ssmod setting*/
ssmod_downspread = <0>;
ssmod_div = <0>;
ssmod_spread = <0>;
/* 2T mode */
mode_2t = <IGNORE_THIS>;
/* speed bin */
speed_bin = <DDR4_DEFAULT>;
/* dram extended temperature support */
dram_ext_temp = <0>;
/* byte map */
byte_map = <((0x2 << 6) | (0x3 << 4) | (0x0 << 2) | (0x1 << 0))>;
/* dq map */
dq_map_cs0_dq_l = <(((3 << 0 | 0 << 2 | 3 << 4 | 1 << 6) << 0) | \
((2 << 0 | 0 << 2 | 2 << 4 | 1 << 6) << 8) | \
((3 << 0 | 2 << 2 | 1 << 4 | 2 << 6) << 16) | \
((3 << 0 | 0 << 2 | 1 << 4 | 0 << 6) << 24))>;
dq_map_cs0_dq_h = <(((2 << 0 | 0 << 2 | 0 << 4 | 1 << 6) << 0) | \
((3 << 0 | 3 << 2 | 2 << 4 | 1 << 6) << 8) | \
((1 << 0 | 3 << 2 | 2 << 4 | 0 << 6) << 16) | \
((3 << 0 | 1 << 2 | 2 << 4 | 0 << 6) << 24))>;
dq_map_cs1_dq_l = <(((2 << 0 | 1 << 2 | 2 << 4 | 0 << 6) << 0) | \
((3 << 0 | 1 << 2 | 3 << 4 | 0 << 6) << 8) | \
((2 << 0 | 3 << 2 | 0 << 4 | 3 << 6) << 16) | \
((2 << 0 | 1 << 2 | 0 << 4 | 1 << 6) << 24))>;
dq_map_cs1_dq_h = <(((3 << 0 | 1 << 2 | 1 << 4 | 0 << 6) << 0) | \
((2 << 0 | 2 << 2 | 3 << 4 | 0 << 6) << 8) | \
((0 << 0 | 2 << 2 | 3 << 4 | 1 << 6) << 16) | \
((2 << 0 | 0 << 2 | 3 << 4 | 1 << 6) << 24))>;
};
lpddr2_params: lpddr2-params {
/* version information */
version = <0x101>;
expanded_version = <IGNORE_THIS>;
reserved = <IGNORE_THIS>;
/* freq info, freq_0 is final frequency, unit: MHz */
freq_0 = <528>;
freq_1 = <328>;
freq_2 = <450>;
freq_3 = <528>;
freq_4 = <IGNORE_THIS>;
freq_5 = <IGNORE_THIS>;
/* power save setting */
pd_idle = <13>;
sr_idle = <93>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
pd_dis_freq = <1066>;
sr_dis_freq = <800>;
dram_dll_dis_freq = <IGNORE_THIS>;
phy_dll_dis_freq = <IGNORE_THIS>;
/* drv when odt on */
phy_dq_drv_odten = <33>;
phy_ca_drv_odten = <33>;
phy_clk_drv_odten = <33>;
dram_dq_drv_odten = <34>;
/* drv when odt off */
phy_dq_drv_odtoff = <33>;
phy_ca_drv_odtoff = <33>;
phy_clk_drv_odtoff = <33>;
dram_dq_drv_odtoff = <34>;
/* odt info */
dram_odt = <0>;
phy_odt = <0>;
phy_odt_puup_en = <0>;
phy_odt_pudn_en = <0>;
/* odt enable freq */
dram_dq_odt_en_freq = <625>;
phy_odt_en_freq = <625>;
/* slew rate when odt enable */
phy_dq_sr_odten = <0xe>;
phy_ca_sr_odten = <0x1>;
phy_clk_sr_odten = <0x1>;
/* slew rate when odt disable */
phy_dq_sr_odtoff = <0xe>;
phy_ca_sr_odtoff = <0x1>;
phy_clk_sr_odtoff = <0x1>;
/* ssmod setting*/
ssmod_downspread = <0>;
ssmod_div = <0>;
ssmod_spread = <0>;
/* 2T mode */
mode_2t = <IGNORE_THIS>;
/* speed bin */
speed_bin = <IGNORE_THIS>;
/* dram extended temperature support */
dram_ext_temp = <0>;
/* byte map */
byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>;
/* dq map */
dq_map_cs0_dq_l = <0>;
dq_map_cs0_dq_h = <0>;
dq_map_cs1_dq_l = <0>;
dq_map_cs1_dq_h = <0>;
};
lpddr3_params: lpddr3-params {
/* version information */
version = <0x101>;
expanded_version = <IGNORE_THIS>;
reserved = <IGNORE_THIS>;
/* freq info, freq_0 is final frequency, unit: MHz */
freq_0 = <786>;
freq_1 = <328>;
freq_2 = <666>;
freq_3 = <786>;
freq_4 = <IGNORE_THIS>;
freq_5 = <IGNORE_THIS>;
/* power save setting */
pd_idle = <13>;
sr_idle = <93>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
pd_dis_freq = <1066>;
sr_dis_freq = <800>;
dram_dll_dis_freq = <IGNORE_THIS>;
phy_dll_dis_freq = <IGNORE_THIS>;
/* drv when odt on */
phy_dq_drv_odten = <33>;
phy_ca_drv_odten = <33>;
phy_clk_drv_odten = <33>;
dram_dq_drv_odten = <34>;
/* drv when odt off */
phy_dq_drv_odtoff = <33>;
phy_ca_drv_odtoff = <33>;
phy_clk_drv_odtoff = <33>;
dram_dq_drv_odtoff = <34>;
/* odt info */
dram_odt = <240>;
phy_odt = <121>;
phy_odt_puup_en = <1>;
phy_odt_pudn_en = <1>;
/* odt enable freq */
dram_dq_odt_en_freq = <333>;
phy_odt_en_freq = <333>;
/* slew rate when odt enable */
phy_dq_sr_odten = <0x0>;
phy_ca_sr_odten = <0x0>;
phy_clk_sr_odten = <0x0>;
/* slew rate when odt disable */
phy_dq_sr_odtoff = <0x0>;
phy_ca_sr_odtoff = <0x0>;
phy_clk_sr_odtoff = <0x0>;
/* ssmod setting*/
ssmod_downspread = <0>;
ssmod_div = <0>;
ssmod_spread = <0>;
/* 2T mode */
mode_2t = <IGNORE_THIS>;
/* speed bin */
speed_bin = <IGNORE_THIS>;
/* dram extended temperature support */
dram_ext_temp = <0>;
/* byte map */
byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>;
/* dq map */
dq_map_cs0_dq_l = <0>;
dq_map_cs0_dq_h = <0>;
dq_map_cs1_dq_l = <0>;
dq_map_cs1_dq_h = <0>;
};
lpddr4_params: lpddr4-params {
/* version information */
version = <0x101>;
expanded_version = <IGNORE_THIS>;
reserved = <IGNORE_THIS>;
/* freq info, freq_0 is final frequency, unit: MHz */
freq_0 = <924>;
freq_1 = <328>;
freq_2 = <666>;
freq_3 = <786>;
freq_4 = <IGNORE_THIS>;
freq_5 = <IGNORE_THIS>;
/* power save setting */
pd_idle = <13>;
sr_idle = <93>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
pd_dis_freq = <1066>;
sr_dis_freq = <800>;
dram_dll_dis_freq = <IGNORE_THIS>;
phy_dll_dis_freq = <IGNORE_THIS>;
/* drv when odt on */
phy_dq_drv_odten = <35>;
phy_ca_drv_odten = <51>;
phy_clk_drv_odten = <47>;
dram_dq_drv_odten = <40>;
/* drv when odt off */
phy_dq_drv_odtoff = <35>;
phy_ca_drv_odtoff = <51>;
phy_clk_drv_odtoff = <47>;
dram_dq_drv_odtoff = <40>;
/* odt info */
dram_odt = <60>;
phy_odt = <80>;
phy_odt_puup_en = <IGNORE_THIS>;
phy_odt_pudn_en = <IGNORE_THIS>;
/* odt enable freq */
dram_dq_odt_en_freq = <800>;
phy_odt_en_freq = <800>;
/* slew rate when odt enable */
phy_dq_sr_odten = <0xf>;
phy_ca_sr_odten = <0x0>;
phy_clk_sr_odten = <0x0>;
/* slew rate when odt disable */
phy_dq_sr_odtoff = <0xf>;
phy_ca_sr_odtoff = <0x0>;
phy_clk_sr_odtoff = <0x0>;
/* ssmod setting*/
ssmod_downspread = <0>;
ssmod_div = <0>;
ssmod_spread = <0>;
/* 2T mode */
mode_2t = <IGNORE_THIS>;
/* speed bin */
speed_bin = <IGNORE_THIS>;
/* dram extended temperature support */
dram_ext_temp = <0>;
/* byte map */
byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>;
/* dq map */
dq_map_cs0_dq_l = <0>;
dq_map_cs0_dq_h = <0>;
dq_map_cs1_dq_l = <0>;
dq_map_cs1_dq_h = <0>;
/* lp4 odt info */
lp4_ca_odt = <60>;
lp4_drv_pu_cal_odten = <LP4_VDDQ_2_5>;
lp4_drv_pu_cal_odtoff = <LP4_VDDQ_2_5>;
phy_lp4_drv_pulldown_en_odten = <0>;
phy_lp4_drv_pulldown_en_odtoff = <0>;
/* lp4 odt enable freq */
lp4_ca_odt_en_freq = <800>;
/* lp4 cs drv info and ca odt info */
phy_lp4_cs_drv_odten = <0>;
phy_lp4_cs_drv_odtoff = <0>;
lp4_odte_ck_en = <1>;
lp4_odte_cs_en = <1>;
lp4_odtd_ca_en = <0>;
/* lp4 vref info when odt enable */
phy_lp4_dq_vref_odten = <200>;
lp4_dq_vref_odten = <316>;
lp4_ca_vref_odten = <420>; /* CA ODT pins have no action */
/* lp4 vref info when odt disable */
phy_lp4_dq_vref_odtoff = <300>;
lp4_dq_vref_odtoff = <420>;
lp4_ca_vref_odtoff = <420>;
};
};

4
arch/arm64/boot/dts/rockchip/rk3326-863-lp3-v10.dtsi
View File

@@ -397,7 +397,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -411,7 +411,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;

4
arch/arm64/boot/dts/rockchip/rk3326-86v-v10.dts
View File

@@ -327,7 +327,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -341,7 +341,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;

4
arch/arm64/boot/dts/rockchip/rk3326-evb-ai-va-v10.dts
View File

@@ -442,7 +442,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -456,7 +456,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;

4
arch/arm64/boot/dts/rockchip/rk3326-evb-ai-va-v11-i2s-dmic.dts
View File

@@ -452,7 +452,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -466,7 +466,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;

4
arch/arm64/boot/dts/rockchip/rk3326-evb-ai-va-v11.dts
View File

@@ -442,7 +442,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -456,7 +456,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;

4
arch/arm64/boot/dts/rockchip/rk3326-evb-ai-va-v12.dts
View File

@@ -442,7 +442,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -456,7 +456,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;

267
arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10-linux.dts
View File

@@ -214,12 +214,12 @@
reg = <0>;
backlight = <&backlight>;
power-supply = <&vcc18_lcd_n>;
prepare-delay-ms = <2>;
reset-delay-ms = <1>;
init-delay-ms = <20>;
enable-delay-ms = <120>;
disable-delay-ms = <50>;
unprepare-delay-ms = <20>;
prepare-delay-ms = <0>;
reset-delay-ms = <0>;
init-delay-ms = <80>;
enable-delay-ms = <0>;
disable-delay-ms = <10>;
unprepare-delay-ms = <60>;
width-mm = <68>;
height-mm = <121>;
@@ -230,46 +230,212 @@
dsi,lanes = <4>;
panel-init-sequence = [
05 fa 01 11
39 00 04 b9 f1 12 83
39 00 1c ba 33 81 05 f9 0e 0e 00 00 00
00 00 00 00 00 44 25 00 91 0a
00 00 02 4f 01 00 00 37
15 00 02 b8 25
39 00 04 bf 02 11 00
39 00 0b b3 0c 10 0a 50 03 ff 00 00 00
00
39 00 0a c0 73 73 50 50 00 00 08 70 00
15 00 02 bc 46
15 00 02 cc 0b
15 00 02 b4 80
39 00 04 b2 c8 12 30
39 00 0f e3 07 07 0b 0b 03 0b 00 00 00
00 ff 00 c0 10
39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67
77 33 33
39 00 07 c6 00 00 ff ff 01 ff
39 00 03 b5 09 09
39 00 03 b6 87 95
39 00 40 e9 c2 10 05 05 10 05 a0 12 31
23 3f 81 0a a0 37 18 00 80 01
00 00 00 00 80 01 00 00 00 48
f8 86 42 08 88 88 80 88 88 88
58 f8 87 53 18 88 88 81 88 88
88 00 00 00 01 00 00 00 00 00
00 00 00 00
39 00 3e ea 00 1a 00 00 00 00 02 00 00
00 00 00 1f 88 81 35 78 88 88
85 88 88 88 0f 88 80 24 68 88
88 84 88 88 88 23 10 00 00 1c
00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 30 05 a0 00 00
00 00
39 00 23 e0 00 06 08 2a 31 3f 38 36 07
0c 0d 11 13 12 13 11 18 00 06
08 2a 31 3f 38 36 07 0c 0d 11
13 12 13 11 18
05 32 01 29
39 00 04 ff 98 81 03
15 00 02 01 00
15 00 02 02 00
15 00 02 03 53
15 00 02 04 53
15 00 02 05 13
15 00 02 06 04
15 00 02 07 02
15 00 02 08 02
15 00 02 09 00
15 00 02 0a 00
15 00 02 0b 00
15 00 02 0c 00
15 00 02 0d 00
15 00 02 0e 00
15 00 02 0f 00
15 00 02 10 00
15 00 02 11 00
15 00 02 12 00
15 00 02 13 00
15 00 02 14 00
15 00 02 15 08
15 00 02 16 10
15 00 02 17 00
15 00 02 18 08
15 00 02 19 00
15 00 02 1a 00
15 00 02 1b 00
15 00 02 1c 00
15 00 02 1d 00
15 00 02 1e c0
15 00 02 1f 80
15 00 02 20 02
15 00 02 21 09
15 00 02 22 00
15 00 02 23 00
15 00 02 24 00
15 00 02 25 00
15 00 02 26 00
15 00 02 27 00
15 00 02 28 55
15 00 02 29 03
15 00 02 2a 00
15 00 02 2b 00
15 00 02 2c 00
15 00 02 2d 00
15 00 02 2e 00
15 00 02 2f 00
15 00 02 30 00
15 00 02 31 00
15 00 02 32 00
15 00 02 33 00
15 00 02 34 04
15 00 02 35 05
15 00 02 36 05
15 00 02 37 00
15 00 02 38 3c
15 00 02 39 35
15 00 02 3a 00
15 00 02 3b 40
15 00 02 3c 00
15 00 02 3d 00
15 00 02 3e 00
15 00 02 3f 00
15 00 02 40 00
15 00 02 41 88
15 00 02 42 00
15 00 02 43 00
15 00 02 44 1f
15 00 02 50 01
15 00 02 51 23
15 00 02 52 45
15 00 02 53 67
15 00 02 54 89
15 00 02 55 ab
15 00 02 56 01
15 00 02 57 23
15 00 02 58 45
15 00 02 59 67
15 00 02 5a 89
15 00 02 5b ab
15 00 02 5c cd
15 00 02 5d ef
15 00 02 5e 03
15 00 02 5f 14
15 00 02 60 15
15 00 02 61 0c
15 00 02 62 0d
15 00 02 63 0e
15 00 02 64 0f
15 00 02 65 10
15 00 02 66 11
15 00 02 67 08
15 00 02 68 02
15 00 02 69 0a
15 00 02 6a 02
15 00 02 6b 02
15 00 02 6c 02
15 00 02 6d 02
15 00 02 6e 02
15 00 02 6f 02
15 00 02 70 02
15 00 02 71 02
15 00 02 72 06
15 00 02 73 02
15 00 02 74 02
15 00 02 75 14
15 00 02 76 15
15 00 02 77 0f
15 00 02 78 0e
15 00 02 79 0d
15 00 02 7a 0c
15 00 02 7b 11
15 00 02 7c 10
15 00 02 7d 06
15 00 02 7e 02
15 00 02 7f 0a
15 00 02 80 02
15 00 02 81 02
15 00 02 82 02
15 00 02 83 02
15 00 02 84 02
15 00 02 85 02
15 00 02 86 02
15 00 02 87 02
15 00 02 88 08
15 00 02 89 02
15 00 02 8a 02
39 00 04 ff 98 81 04
15 00 02 00 80
15 00 02 70 00
15 00 02 71 00
15 00 02 66 fe
15 00 02 82 15
15 00 02 84 15
15 00 02 85 15
15 00 02 3a 24
15 00 02 32 ac
15 00 02 8c 80
15 00 02 3c f5
15 00 02 88 33
39 00 04 ff 98 81 01
15 00 02 22 0a
15 00 02 31 00
15 00 02 53 78
15 00 02 50 5b
15 00 02 51 5b
15 00 02 60 20
15 00 02 61 00
15 00 02 62 0d
15 00 02 63 00
15 00 02 a0 00
15 00 02 a1 10
15 00 02 a2 1c
15 00 02 a3 13
15 00 02 a4 15
15 00 02 a5 26
15 00 02 a6 1a
15 00 02 a7 1d
15 00 02 a8 67
15 00 02 a9 1c
15 00 02 aa 29
15 00 02 ab 5b
15 00 02 ac 26
15 00 02 ad 28
15 00 02 ae 5c
15 00 02 af 30
15 00 02 b0 31
15 00 02 b1 2e
15 00 02 b2 32
15 00 02 b3 00
15 00 02 c0 00
15 00 02 c1 10
15 00 02 c2 1c
15 00 02 c3 13
15 00 02 c4 15
15 00 02 c5 26
15 00 02 c6 1a
15 00 02 c7 1d
15 00 02 c8 67
15 00 02 c9 1c
15 00 02 ca 29
15 00 02 cb 5b
15 00 02 cc 26
15 00 02 cd 28
15 00 02 ce 5c
15 00 02 cf 30
15 00 02 d0 31
15 00 02 d1 2e
15 00 02 d2 32
15 00 02 d3 00
39 00 04 ff 98 81 00
05 00 01 11
05 01 01 29
];
panel-exit-sequence = [
@@ -451,7 +617,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -465,7 +631,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -758,6 +924,11 @@
/*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/
pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "TongJu";
rockchip,camera-module-lens-name = "CHT842-MD";
port {
ucam_out: endpoint {
remote-endpoint = <&mipi_in_ucam>;

4
arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10-robot-linux.dts
View File

@@ -233,7 +233,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -247,7 +247,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;

4
arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10-robot-no-gpu-linux.dts
View File

@@ -228,7 +228,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -242,7 +242,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;

4
arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10.dtsi
View File

@@ -436,7 +436,7 @@
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
@@ -450,7 +450,7 @@
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;

3
arch/arm64/configs/px30_linux_defconfig
View File

@@ -53,6 +53,7 @@ CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPUFREQ_DT=y
CONFIG_ARM_ROCKCHIP_CPUFREQ=y
CONFIG_ARM_SCMI_PROTOCOL=y
CONFIG_ROCKCHIP_SIP=y
CONFIG_PARTITION_ADVANCED=y
# CONFIG_COMPACTION is not set
@@ -344,6 +345,8 @@ CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y
CONFIG_RK_CONSOLE_THREAD=y
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
CONFIG_MAILBOX=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_CPU_PX30=y
CONFIG_ROCKCHIP_PM_DOMAINS=y

3
arch/arm64/configs/rk3326_linux_defconfig
View File

@@ -53,6 +53,7 @@ CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPUFREQ_DT=y
CONFIG_ARM_ROCKCHIP_CPUFREQ=y
CONFIG_ARM_SCMI_PROTOCOL=y
CONFIG_ROCKCHIP_SIP=y
CONFIG_PARTITION_ADVANCED=y
# CONFIG_COMPACTION is not set
@@ -341,6 +342,8 @@ CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y
CONFIG_RK_CONSOLE_THREAD=y
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
CONFIG_MAILBOX=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_CPU_PX30=y
CONFIG_ROCKCHIP_PM_DOMAINS=y

52
drivers/clk/rockchip/clk-px30.c
View File

@@ -16,6 +16,7 @@
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/rockchip/cpu.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/px30-cru.h>
#include "clk.h"
@@ -156,6 +157,7 @@ PNAME(mux_npll_cpll_p) = { "npll", "cpll" };
PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" };
PNAME(mux_gpll_npll_p) = { "gpll", "dummy_npll" };
PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m"};
PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll"};
PNAME(mux_gpll_cpll_npll_p) = { "gpll", "dummy_cpll", "dummy_npll" };
PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "dummy_cpll", "dummy_npll", "xin24m" };
PNAME(mux_gpll_xin24m_npll_p) = { "gpll", "xin24m", "dummy_npll"};
@@ -337,12 +339,6 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p,
CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(2), 7, 1, 0, 3,
ROCKCHIP_DDRCLK_SIP_V2),
COMPOSITE_NOGATE(0, "clk_ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS),
FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
PX30_CLKGATE_CON(0), 14, GFLAGS),
FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
PX30_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(2), 4, 1, MFLAGS,
PX30_CLKGATE_CON(1), 13, GFLAGS),
@@ -769,12 +765,6 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
PX30_CLKSEL_CON(55), 0, 11, DFLAGS,
PX30_CLKGATE_CON(12), 10, GFLAGS),
COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,
PX30_CLKSEL_CON(56), 0, 3, DFLAGS,
PX30_CLKGATE_CON(12), 11, GFLAGS),
COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0,
PX30_CLKSEL_CON(56), 4, 2, DFLAGS,
PX30_CLKGATE_CON(13), 6, GFLAGS),
GATE(0, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(12), 12, GFLAGS),
@@ -1004,6 +994,36 @@ static const char *const px30_pmucru_critical_clocks[] __initconst = {
"pclk_uart2",
};
static struct rockchip_clk_branch px30_clk_ddrphy_otp[] __initdata = {
COMPOSITE_NOGATE(0, "clk_ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS),
FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
PX30_CLKGATE_CON(0), 14, GFLAGS),
FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy4x",
CLK_IGNORE_UNUSED, 1, 4,
PX30_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,
PX30_CLKSEL_CON(56), 0, 3, DFLAGS,
PX30_CLKGATE_CON(12), 11, GFLAGS),
COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0,
PX30_CLKSEL_CON(56), 4, 2, DFLAGS,
PX30_CLKGATE_CON(13), 6, GFLAGS),
};
static struct rockchip_clk_branch px30s_clk_ddrphy_otp[] __initdata = {
COMPOSITE(0, "clk_ddrphy1x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS,
PX30_CLKGATE_CON(0), 14, GFLAGS),
FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy1x",
CLK_IGNORE_UNUSED, 1, 4,
PX30_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE(SCLK_OTP_USR, "clk_otp_usr", mux_xin24m_gpll_p, 0,
PX30_CLKSEL_CON(56), 8, 1, MFLAGS, 0, 8, DFLAGS,
PX30_CLKGATE_CON(12), 11, GFLAGS),
};
static void __init px30_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
@@ -1043,6 +1063,14 @@ static void __init px30_clk_init(struct device_node *np)
rockchip_clk_register_branches(ctx, rk3326_gpu_src_clk,
ARRAY_SIZE(rk3326_gpu_src_clk));
rockchip_soc_id_init();
if (soc_is_px30s())
rockchip_clk_register_branches(ctx, px30s_clk_ddrphy_otp,
ARRAY_SIZE(px30s_clk_ddrphy_otp));
else
rockchip_clk_register_branches(ctx, px30_clk_ddrphy_otp,
ARRAY_SIZE(px30_clk_ddrphy_otp));
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
&px30_cpuclk_data, px30_cpuclk_rates,

5
drivers/gpu/arm/bifrost/backend/gpu/mali_kbase_devfreq.c
View File

@@ -34,6 +34,7 @@
#include <linux/version.h>
#include <linux/pm_opp.h>
#include <linux/pm_runtime.h>
#include <soc/rockchip/rockchip_ipa.h>
#include <soc/rockchip/rockchip_opp_select.h>
@@ -227,6 +228,8 @@ kbase_devfreq_target(struct device *dev, unsigned long *target_freq, u32 flags)
}
#endif
/* enable pd for pvtpll clk for px30s/rk3326s */
pm_runtime_get_sync(dev);
for (i = 0; i < kbdev->nr_clocks; i++) {
if (kbdev->clocks[i]) {
int err;
@@ -237,10 +240,12 @@ kbase_devfreq_target(struct device *dev, unsigned long *target_freq, u32 flags)
} else {
dev_err(dev, "Failed to set clock %lu (target %lu)\n",
freqs[i], *target_freq);
pm_runtime_put_sync(dev);
return err;
}
}
}
pm_runtime_put_sync(dev);
#if IS_ENABLED(CONFIG_REGULATOR)
for (i = 0; i < kbdev->nr_clocks; i++) {

14
drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c
View File

@@ -169,11 +169,25 @@ struct kbase_platform_funcs_conf platform_funcs = {
static int rk_pm_callback_runtime_on(struct kbase_device *kbdev)
{
int i;
for (i = 0; i < kbdev->nr_clocks; i++) {
if (kbdev->clocks[i])
clk_set_rate(kbdev->clocks[i], kbdev->current_freqs[i]);
}
return 0;
}
static void rk_pm_callback_runtime_off(struct kbase_device *kbdev)
{
int i;
for (i = 0; i < kbdev->nr_clocks; i++) {
/* switch to normal pll(200M) before disable pd */
if (kbdev->clocks[i])
clk_set_rate(kbdev->clocks[i], 200000000);
}
}
static int rk_pm_callback_power_on(struct kbase_device *kbdev)

177
drivers/nvmem/rockchip-otp.c
View File

@@ -14,6 +14,7 @@
#include <linux/module.h>
#include <linux/nvmem-provider.h>
#include <linux/reset.h>
#include <linux/rockchip/cpu.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_platform.h>
@@ -33,6 +34,25 @@
#define OTPC_SBPI_CMD0_OFFSET 0x1000
#define OTPC_SBPI_CMD1_OFFSET 0x1004
#define OTPC_MODE_CTRL 0x2000
#define OTPC_IRQ_ST 0x2008
#define OTPC_ACCESS_ADDR 0x200c
#define OTPC_RD_DATA 0x2010
#define OTPC_REPR_RD_TRANS_NUM 0x2020
#define OTPC_DEEP_STANDBY 0x0
#define OTPC_STANDBY 0x1
#define OTPC_ACTIVE 0x2
#define OTPC_READ_ACCESS 0x3
#define OTPC_TRANS_NUM 0x1
#define OTPC_RDM_IRQ_ST BIT(0)
#define OTPC_STB2ACT_IRQ_ST BIT(7)
#define OTPC_DP2STB_IRQ_ST BIT(8)
#define OTPC_ACT2STB_IRQ_ST BIT(9)
#define OTPC_STB2DP_IRQ_ST BIT(10)
#define PX30S_NBYTES 4
#define PX30S_NO_SECURE_OFFSET 224
/* OTP Register bits and masks */
#define OTPC_USER_ADDR_MASK GENMASK(31, 16)
#define OTPC_USE_USER BIT(0)
@@ -251,6 +271,150 @@ disable_clks:
return ret;
}
static int px30s_otp_wait_status(struct rockchip_otp *otp, u32 flag)
{
u32 status = 0;
int ret;
ret = readl_poll_timeout_atomic(otp->base + OTPC_IRQ_ST, status,
(status & flag), 1, OTPC_TIMEOUT);
if (ret)
return ret;
/* clean int status */
writel(flag, otp->base + OTPC_IRQ_ST);
return 0;
}
static int px30s_otp_active(struct rockchip_otp *otp)
{
int ret = 0;
u32 mode;
mode = readl(otp->base + OTPC_MODE_CTRL);
switch (mode) {
case OTPC_DEEP_STANDBY:
writel(OTPC_STANDBY, otp->base + OTPC_MODE_CTRL);
ret = px30s_otp_wait_status(otp, OTPC_DP2STB_IRQ_ST);
if (ret < 0) {
dev_err(otp->dev, "timeout during wait dp2stb\n");
return ret;
}
/* fall through */
case OTPC_STANDBY:
writel(OTPC_ACTIVE, otp->base + OTPC_MODE_CTRL);
ret = px30s_otp_wait_status(otp, OTPC_STB2ACT_IRQ_ST);
if (ret < 0) {
dev_err(otp->dev, "timeout during wait stb2act\n");
return ret;
}
break;
default:
break;
}
return ret;
}
static int px30s_otp_standby(struct rockchip_otp *otp)
{
int ret = 0;
u32 mode;
mode = readl(otp->base + OTPC_MODE_CTRL);
switch (mode) {
case OTPC_ACTIVE:
writel(OTPC_STANDBY, otp->base + OTPC_MODE_CTRL);
ret = px30s_otp_wait_status(otp, OTPC_ACT2STB_IRQ_ST);
if (ret < 0) {
dev_err(otp->dev, "timeout during wait act2stb\n");
return ret;
}
/* fall through */
case OTPC_STANDBY:
writel(OTPC_DEEP_STANDBY, otp->base + OTPC_MODE_CTRL);
ret = px30s_otp_wait_status(otp, OTPC_STB2DP_IRQ_ST);
if (ret < 0) {
dev_err(otp->dev, "timeout during wait stb2dp\n");
return ret;
}
break;
default:
break;
}
return ret;
}
static int px30s_otp_read(void *context, unsigned int offset, void *val,
size_t bytes)
{
struct rockchip_otp *otp = context;
unsigned int addr_start, addr_end, addr_offset, addr_len;
int ret, i = 0;
u32 out_value;
u8 *buf;
if (offset >= otp->data->size)
return -ENOMEM;
if (offset + bytes > otp->data->size)
bytes = otp->data->size - offset;
ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks);
if (ret < 0) {
dev_err(otp->dev, "failed to prepare/enable clks\n");
return ret;
}
ret = rockchip_otp_reset(otp);
if (ret) {
dev_err(otp->dev, "failed to reset otp phy\n");
goto disable_clks;
}
ret = px30s_otp_active(otp);
if (ret)
goto disable_clks;
addr_start = rounddown(offset, PX30S_NBYTES) / PX30S_NBYTES;
addr_end = roundup(offset + bytes, PX30S_NBYTES) / PX30S_NBYTES;
addr_offset = offset % PX30S_NBYTES;
addr_len = addr_end - addr_start;
addr_start += PX30S_NO_SECURE_OFFSET;
buf = kzalloc(sizeof(*buf) * addr_len * PX30S_NBYTES, GFP_KERNEL);
if (!buf) {
ret = -ENOMEM;
goto read_end;
}
while (addr_len--) {
writel(OTPC_TRANS_NUM, otp->base + OTPC_REPR_RD_TRANS_NUM);
writel(addr_start++, otp->base + OTPC_ACCESS_ADDR);
writel(OTPC_READ_ACCESS, otp->base + OTPC_MODE_CTRL);
ret = px30s_otp_wait_status(otp, OTPC_RDM_IRQ_ST);
if (ret < 0) {
dev_err(otp->dev, "timeout during wait rd\n");
goto read_end;
}
out_value = readl(otp->base + OTPC_RD_DATA);
memcpy(&buf[i], &out_value, PX30S_NBYTES);
i += PX30S_NBYTES;
}
memcpy(val, buf + addr_offset, (unsigned int)bytes);
read_end:
kfree(buf);
px30s_otp_standby(otp);
disable_clks:
clk_bulk_disable_unprepare(otp->num_clks, otp->clks);
return ret;
}
static int rk3568_otp_read(void *context, unsigned int offset, void *val,
size_t bytes)
{
@@ -504,6 +668,13 @@ static const struct rockchip_data px30_data = {
.reg_read = px30_otp_read,
};
static const struct rockchip_data px30s_data = {
.size = 0x80,
.clocks = px30_otp_clocks,
.num_clks = ARRAY_SIZE(px30_otp_clocks),
.reg_read = px30s_otp_read,
};
static const char * const rk3568_otp_clocks[] = {
"usr", "sbpi", "apb", "phy",
};
@@ -534,6 +705,10 @@ static const struct of_device_id rockchip_otp_match[] = {
.compatible = "rockchip,px30-otp",
.data = (void *)&px30_data,
},
{
.compatible = "rockchip,px30s-otp",
.data = (void *)&px30s_data,
},
#endif
#ifdef CONFIG_CPU_RK3308
{
@@ -570,6 +745,8 @@ static int __init rockchip_otp_probe(struct platform_device *pdev)
dev_err(dev, "failed to get match data\n");
return -EINVAL;
}
if (soc_is_px30s())
data = &px30s_data;
otp = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_otp),
GFP_KERNEL);

72
drivers/phy/rockchip/phy-rockchip-inno-usb2.c
View File

@@ -34,6 +34,7 @@
#include <linux/pm_runtime.h>
#include <linux/power_supply.h>
#include <linux/regmap.h>
#include <linux/rockchip/cpu.h>
#include <linux/mfd/syscon.h>
#include <linux/usb/of.h>
#include <linux/usb/otg.h>
@@ -2152,26 +2153,65 @@ static int rk3328_usb2phy_tuning(struct rockchip_usb2phy *rphy)
{
int ret;
/* Open debug mode for tuning */
ret = regmap_write(rphy->grf, 0x2c, 0xffff0400);
if (ret)
return ret;
if (soc_is_px30s()) {
/* Enable otg port pre-emphasis during non-chirp phase */
ret = regmap_update_bits(rphy->grf, 0x8000, GENMASK(2, 0), BIT(2));
if (ret)
return ret;
/* Open pre-emphasize in non-chirp state for otg port */
ret = regmap_write(rphy->grf, 0x0, 0x00070004);
if (ret)
return ret;
/* Set otg port squelch trigger point configure to 100mv */
ret = regmap_update_bits(rphy->grf, 0x8004, GENMASK(7, 5), 0x40);
if (ret)
return ret;
/* Open pre-emphasize in non-chirp state for host port */
ret = regmap_write(rphy->grf, 0x30, 0x00070004);
if (ret)
return ret;
ret = regmap_update_bits(rphy->grf, 0x8008, BIT(0), 0x1);
if (ret)
return ret;
/* Turn off differential receiver in suspend mode */
ret = regmap_write(rphy->grf, 0x18, 0x00040000);
if (ret)
return ret;
/* Turn off otg port differential reciver in suspend mode */
ret = regmap_update_bits(rphy->grf, 0x8030, BIT(2), 0);
if (ret)
return ret;
/* Enable host port pre-emphasis during non-chirp phase */
ret = regmap_update_bits(rphy->grf, 0x8400, GENMASK(2, 0), BIT(2));
if (ret)
return ret;
/* Set host port squelch trigger point configure to 100mv */
ret = regmap_update_bits(rphy->grf, 0x8404, GENMASK(7, 5), 0x40);
if (ret)
return ret;
ret = regmap_update_bits(rphy->grf, 0x8408, BIT(0), 0x1);
if (ret)
return ret;
/* Turn off host port differential reciver in suspend mode */
ret = regmap_update_bits(rphy->grf, 0x8430, BIT(2), 0);
if (ret)
return ret;
} else {
/* Open debug mode for tuning */
ret = regmap_write(rphy->grf, 0x2c, 0xffff0400);
if (ret)
return ret;
/* Open pre-emphasize in non-chirp state for otg port */
ret = regmap_write(rphy->grf, 0x0, 0x00070004);
if (ret)
return ret;
/* Open pre-emphasize in non-chirp state for host port */
ret = regmap_write(rphy->grf, 0x30, 0x00070004);
if (ret)
return ret;
/* Turn off differential receiver in suspend mode */
ret = regmap_write(rphy->grf, 0x18, 0x00040000);
if (ret)
return ret;
}
return 0;
}

102
drivers/phy/rockchip/phy-rockchip-inno-video-combo-phy.c
View File

@@ -19,6 +19,7 @@
#include <linux/phy/phy.h>
#include <linux/pm_runtime.h>
#include <linux/mfd/syscon.h>
#include <linux/rockchip/cpu.h>
#define PSEC_PER_SEC 1000000000000LL
@@ -196,6 +197,14 @@
#define DSI_PHY_STATUS 0xb0
#define PHY_LOCK BIT(0)
enum soc_type {
PX30,
PX30S,
RK3128,
RK3368,
RK3568,
};
enum phy_max_rate {
MAX_1GHZ,
MAX_2_5GHZ,
@@ -256,6 +265,7 @@ struct inno_video_phy {
};
struct inno_video_phy_plat_data {
enum soc_type soc_type;
const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table;
const unsigned int num_timings;
enum phy_max_rate max_rate;
@@ -590,6 +600,12 @@ static void inno_video_phy_mipi_mode_enable(struct inno_video_phy *inno)
/* Select MIPI mode */
phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
MODE_ENABLE_MASK, MIPI_MODE_ENABLE);
/* set pin_txclkesc_0 pin_txbyteclk invert disable */
if (inno->pdata->soc_type == PX30S)
phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x01,
INVERT_TXCLKESC_MASK, INVERT_TXCLKESC_DISABLE);
if (inno->pdata->max_rate == MAX_2_5GHZ)
inno_mipi_dphy_max_2_5GHz_pll_enable(inno);
else
@@ -614,6 +630,16 @@ static void inno_video_phy_lvds_mode_enable(struct inno_video_phy *inno)
SAMPLE_CLOCK_DIRECTION_MASK | LOWFRE_EN_MASK,
SAMPLE_CLOCK_DIRECTION_REVERSE |
PLL_OUTPUT_FREQUENCY_DIV_BY_1);
/* Reset LVDS digital logic */
phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
LVDS_DIGITAL_INTERNAL_RESET_MASK,
LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
udelay(1);
phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
LVDS_DIGITAL_INTERNAL_RESET_MASK,
LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
/* Select LVDS mode */
phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
MODE_ENABLE_MASK, LVDS_MODE_ENABLE);
@@ -638,14 +664,6 @@ static void inno_video_phy_lvds_mode_enable(struct inno_video_phy *inno)
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e,
PLL_MODE_SEL_MASK, PLL_MODE_SEL_LVDS_MODE);
/* Reset LVDS digital logic */
phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
LVDS_DIGITAL_INTERNAL_RESET_MASK,
LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
udelay(1);
phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
LVDS_DIGITAL_INTERNAL_RESET_MASK,
LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
/* Enable LVDS digital logic */
phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
@@ -659,9 +677,6 @@ static void inno_video_phy_lvds_mode_enable(struct inno_video_phy *inno)
static void inno_video_phy_ttl_mode_enable(struct inno_video_phy *inno)
{
/* Select TTL mode */
phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
MODE_ENABLE_MASK, TTL_MODE_ENABLE);
/* Reset digital logic */
phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
LVDS_DIGITAL_INTERNAL_RESET_MASK,
@@ -670,6 +685,10 @@ static void inno_video_phy_ttl_mode_enable(struct inno_video_phy *inno)
phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
LVDS_DIGITAL_INTERNAL_RESET_MASK,
LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
/* Select TTL mode */
phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
MODE_ENABLE_MASK, TTL_MODE_ENABLE);
/* Enable digital logic */
phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
@@ -929,6 +948,41 @@ static const struct regmap_config inno_video_phy_regmap_config = {
.max_register = 0x3ac,
};
static const struct inno_video_phy_plat_data px30_video_phy_plat_data = {
.soc_type = PX30,
.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz,
.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz),
.max_rate = MAX_1GHZ,
};
static const struct inno_video_phy_plat_data px30s_video_phy_plat_data = {
.soc_type = PX30S,
.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz,
.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz),
.max_rate = MAX_2_5GHZ,
};
static const struct inno_video_phy_plat_data rk3128_video_phy_plat_data = {
.soc_type = RK3128,
.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz,
.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz),
.max_rate = MAX_1GHZ,
};
static const struct inno_video_phy_plat_data rk3368_video_phy_plat_data = {
.soc_type = RK3368,
.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz,
.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz),
.max_rate = MAX_1GHZ,
};
static const struct inno_video_phy_plat_data rk3568_video_phy_plat_data = {
.soc_type = RK3568,
.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz,
.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz),
.max_rate = MAX_2_5GHZ,
};
static int inno_video_phy_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -945,6 +999,9 @@ static int inno_video_phy_probe(struct platform_device *pdev)
inno->dev = dev;
inno->pdata = of_device_get_match_data(inno->dev);
if (soc_is_px30s())
inno->pdata = &px30s_video_phy_plat_data;
platform_set_drvdata(pdev, inno);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1041,31 +1098,22 @@ static int inno_video_phy_remove(struct platform_device *pdev)
return 0;
}
static const struct inno_video_phy_plat_data phy_max_1GHz_plat_data = {
.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz,
.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz),
.max_rate = MAX_1GHZ,
};
static const struct inno_video_phy_plat_data phy_max_2_5GHz_plat_data = {
.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz,
.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz),
.max_rate = MAX_2_5GHZ,
};
static const struct of_device_id inno_video_phy_of_match[] = {
{
.compatible = "rockchip,px30-video-phy",
.data = &phy_max_1GHz_plat_data,
.data = &px30_video_phy_plat_data,
}, {
.compatible = "rockchip,px30s-video-phy",
.data = &px30s_video_phy_plat_data,
}, {
.compatible = "rockchip,rk3128-video-phy",
.data = &phy_max_1GHz_plat_data,
.data = &rk3128_video_phy_plat_data,
}, {
.compatible = "rockchip,rk3368-video-phy",
.data = &phy_max_1GHz_plat_data,
.data = &rk3368_video_phy_plat_data,
}, {
.compatible = "rockchip,rk3568-video-phy",
.data = &phy_max_2_5GHz_plat_data,
.data = &rk3568_video_phy_plat_data,
},
{}
};

64
drivers/phy/rockchip/phy-rockchip-mipi-rx.c
View File

@@ -48,6 +48,7 @@
#include <media/v4l2-fwnode.h>
#include <media/v4l2-subdev.h>
#include <media/v4l2-device.h>
#include <linux/rockchip/cpu.h>
/* GRF */
#define RK1808_GRF_PD_VI_CON_OFFSET 0x0430
@@ -146,6 +147,17 @@
#define RK3326_CSI_DPHY_LANE3_WR_THS_SETTLE \
(RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
#define RK3326S_CSI_DPHY_CLK_WR_THS_SETTLE 0x160
#define RK3326S_CSI_DPHY_LANE0_WR_THS_SETTLE \
(RK3326S_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
#define RK3326S_CSI_DPHY_LANE1_WR_THS_SETTLE \
(RK3326S_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
#define RK3326S_CSI_DPHY_LANE2_WR_THS_SETTLE \
(RK3326S_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
#define RK3326S_CSI_DPHY_LANE3_WR_THS_SETTLE \
(RK3326S_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
#define RK3326S_CSI_DPHY_CLK_MODE 0x128
#define RK3368_CSI_DPHY_CLK_WR_THS_SETTLE 0x100
#define RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE \
(RK3368_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
@@ -218,6 +230,7 @@ enum mipi_dphy_chip_id {
CHIP_ID_RK3368,
CHIP_ID_RK3399,
CHIP_ID_RK1126,
CHIP_ID_RK3326S,
};
enum mipi_dphy_rx_pads {
@@ -287,6 +300,7 @@ enum csiphy_reg_id {
//rv1126 only
CSIPHY_MIPI_LVDS_MODEL,
CSIPHY_LVDS_MODE,
CSIPHY_CLK_MODE,
};
enum mipi_dphy_ctl_type {
@@ -473,6 +487,23 @@ static const struct csiphy_reg rk3326_csiphy_regs[] = {
[CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE3_CALIB_EN),
};
static const struct csiphy_reg rk3326s_csiphy_regs[] = {
[CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_LANE_ENABLE),
[CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_PWRCTL),
[CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_DIG_RST),
[CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK3326S_CSI_DPHY_CLK_WR_THS_SETTLE),
[CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK3326S_CSI_DPHY_LANE0_WR_THS_SETTLE),
[CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK3326S_CSI_DPHY_LANE1_WR_THS_SETTLE),
[CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK3326S_CSI_DPHY_LANE2_WR_THS_SETTLE),
[CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK3326S_CSI_DPHY_LANE3_WR_THS_SETTLE),
[CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_CLK_CALIB_EN),
[CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE0_CALIB_EN),
[CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE1_CALIB_EN),
[CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE2_CALIB_EN),
[CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE3_CALIB_EN),
[CSIPHY_CLK_MODE] = CSIPHY_REG(RK3326S_CSI_DPHY_CLK_MODE),
};
static const struct csiphy_reg rk3368_csiphy_regs[] = {
[CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_CTRL_LANE_ENABLE),
[CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK3368_CSI_DPHY_CTRL_PWRCTL),
@@ -1011,6 +1042,12 @@ static const struct hsfreq_range rk3326_mipidphy_hsfreq_ranges[] = {
{1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}
};
static const struct hsfreq_range rk3326s_mipidphy_hsfreq_ranges[] = {
{ 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06},
{ 299, 0x06}, { 399, 0x08}, { 499, 0x0b}, { 599, 0x0e},
{ 699, 0x10}, { 799, 0x12}, { 999, 0x16}, {1199, 0x1e},
};
static const struct hsfreq_range rk3368_mipidphy_hsfreq_ranges[] = {
{ 109, 0x00}, { 149, 0x01}, { 199, 0x02}, { 249, 0x03},
{ 299, 0x04}, { 399, 0x05}, { 499, 0x06}, { 599, 0x07},
@@ -1325,6 +1362,7 @@ static int csi_mipidphy_stream_on(struct mipidphy_priv *priv,
int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
int i, hsfreq = 0;
u32 val = 0;
u32 clk_mode = 0x03;
write_grf_reg(priv, GRF_DVP_V18SEL, 0x1);
@@ -1344,6 +1382,13 @@ static int csi_mipidphy_stream_on(struct mipidphy_priv *priv,
/* Reset dphy digital part */
write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x1e);
write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x1f);
if (drv_data->chip_id == CHIP_ID_RK3326S) {
if (sensor->mbus.flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK)
clk_mode = 0x03;
else if (sensor->mbus.flags & V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK)
clk_mode = 0;
write_csiphy_reg(priv, CSIPHY_CLK_MODE, clk_mode);
}
} else {
/* Disable MIPI internal logical and switch to LVDS bank */
write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x3e);
@@ -1467,6 +1512,18 @@ static const struct dphy_drv_data rk3326_mipidphy_drv_data = {
.chip_id = CHIP_ID_RK3326,
};
static const struct dphy_drv_data rk3326s_mipidphy_drv_data = {
.clks = rk3326_mipidphy_clks,
.num_clks = ARRAY_SIZE(rk3326_mipidphy_clks),
.hsfreq_ranges = rk3326s_mipidphy_hsfreq_ranges,
.num_hsfreq_ranges = ARRAY_SIZE(rk3326s_mipidphy_hsfreq_ranges),
.grf_regs = rk3326_grf_dphy_regs,
.csiphy_regs = rk3326s_csiphy_regs,
.ctl_type = MIPI_DPHY_CTL_CSI_HOST,
.individual_init = default_mipidphy_individual_init,
.chip_id = CHIP_ID_RK3326S,
};
static const struct dphy_drv_data rk3368_mipidphy_drv_data = {
.clks = rk3368_mipidphy_clks,
.num_clks = ARRAY_SIZE(rk3368_mipidphy_clks),
@@ -1515,6 +1572,10 @@ static const struct of_device_id rockchip_mipidphy_match_id[] = {
.compatible = "rockchip,rk3326-mipi-dphy",
.data = &rk3326_mipidphy_drv_data,
},
{
.compatible = "rockchip,rk3326s-mipi-dphy",
.data = &rk3326s_mipidphy_drv_data,
},
{
.compatible = "rockchip,rk3368-mipi-dphy",
.data = &rk3368_mipidphy_drv_data,
@@ -1719,6 +1780,9 @@ static int rockchip_mipidphy_probe(struct platform_device *pdev)
priv->phy_index = 0;
drv_data = of_id->data;
if (soc_is_px30s())
drv_data = &rk3326s_mipidphy_drv_data;
for (i = 0; i < drv_data->num_clks; i++) {
priv->clks[i] = devm_clk_get(dev, drv_data->clks[i]);

76
drivers/pinctrl/pinctrl-rockchip.c
View File

@@ -204,6 +204,12 @@
.route_location = FLAG, \
}
#define PX30S_PIN_BANK_FLAGS(ID, PIN, LABEL, MTYPE, DTYPE) \
PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(ID, PIN, LABEL, \
MTYPE, MTYPE, MTYPE, MTYPE, \
DTYPE, DTYPE, DTYPE, DTYPE, \
-1, -1, -1, -1)
#define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \
PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
@@ -2103,7 +2109,8 @@ static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
{ 3, 6, 9, 12, -1, -1, -1, -1 },
{ 5, 10, 15, 20, -1, -1, -1, -1 },
{ 4, 6, 8, 10, 12, 14, 16, 18 },
{ 4, 7, 10, 13, 16, 19, 22, 26 }
{ 4, 7, 10, 13, 16, 19, 22, 26 },
{ 0, 2, 4, 6, 6, 8, 10, 12 }
};
static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
@@ -2165,6 +2172,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
case DRV_TYPE_IO_SMIC:
rmask_bits = RK3288_DRV_BITS_PER_PIN;
break;
default:
@@ -2180,6 +2188,20 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
data >>= bit;
data &= (1 << rmask_bits) - 1;
if (drv_type == DRV_TYPE_IO_SMIC) {
u32 tmp = 0;
ctrl->slew_rate_calc_reg(bank, pin_num, &regmap, &reg, &bit);
ret = regmap_read(regmap, reg, &tmp);
if (ret)
return ret;
tmp >>= bit;
tmp &= 0x1;
data |= tmp << 2;
}
return rockchip_perpin_drv_list[drv_type][data];
}
@@ -2189,7 +2211,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret, i;
int reg, ret, i, err;
u32 data, rmask, rmask_bits, temp;
u8 bit;
int drv_type = bank->drv[pin_num / 8].drv_type;
@@ -2244,16 +2266,16 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
rmask = BIT(15) | BIT(31);
data |= BIT(31);
ret = regmap_update_bits(regmap, reg, rmask, data);
if (ret)
return ret;
err = regmap_update_bits(regmap, reg, rmask, data);
if (err)
return err;
rmask = 0x3 | (0x3 << 16);
temp |= (0x3 << 16);
reg += 0x4;
ret = regmap_update_bits(regmap, reg, rmask, temp);
err = regmap_update_bits(regmap, reg, rmask, temp);
return ret;
return err;
case 18 ... 21:
/* setting fully enclosed in the second register */
reg += 4;
@@ -2268,6 +2290,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
case DRV_TYPE_IO_SMIC:
rmask_bits = RK3288_DRV_BITS_PER_PIN;
break;
default:
@@ -2282,9 +2305,9 @@ config:
rmask = data | (data >> 16);
data |= (ret << bit);
ret = regmap_update_bits(regmap, reg, rmask, data);
if (ret)
return ret;
err = regmap_update_bits(regmap, reg, rmask, data);
if (err)
return err;
if (ctrl->type == RK3568 && rockchip_get_cpu_version() == 0) {
if (bank->bank_num == 1 && pin_num == 21)
@@ -2306,9 +2329,17 @@ config:
rmask = data | (data >> 16);
data |= (1 << (strength + 1)) - 1;
ret = regmap_update_bits(regmap, reg, rmask, data);
if (ret)
return ret;
err = regmap_update_bits(regmap, reg, rmask, data);
if (err)
return err;
}
if (drv_type == DRV_TYPE_IO_SMIC) {
ctrl->slew_rate_calc_reg(bank, pin_num, &regmap, &reg, &bit);
data = BIT(bit + 16) | (((ret >> 2) & 0x1) << bit);
err = regmap_write(regmap, reg, data);
if (err)
return err;
}
return 0;
@@ -2622,6 +2653,10 @@ static int rockchip_get_slew_rate(struct rockchip_pin_bank *bank, int pin_num)
int reg, ret;
u8 bit;
u32 data;
int drv_type = bank->drv[pin_num / 8].drv_type;
if (drv_type == DRV_TYPE_IO_SMIC)
return 0;
ret = ctrl->slew_rate_calc_reg(bank, pin_num, &regmap, &reg, &bit);
if (ret)
@@ -2644,6 +2679,10 @@ static int rockchip_set_slew_rate(struct rockchip_pin_bank *bank,
int reg, ret;
u8 bit;
u32 data, rmask;
int drv_type = bank->drv[pin_num / 8].drv_type;
if (drv_type == DRV_TYPE_IO_SMIC)
return 0;
dev_dbg(info->dev, "setting slew rate of GPIO%d-%d to %d\n",
bank->bank_num, pin_num, speed);
@@ -3188,6 +3227,8 @@ static int rk3308b_ctrl_data_re_init(struct rockchip_pin_ctrl *ctrl)
return 0;
}
static struct rockchip_pin_bank px30s_pin_banks[];
/* retrieve the soc specific data */
static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
struct rockchip_pinctrl *d,
@@ -3201,6 +3242,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
match = of_match_node(rockchip_pinctrl_dt_match, node);
ctrl = (struct rockchip_pin_ctrl *)match->data;
if (IS_ENABLED(CONFIG_CPU_PX30) && soc_is_px30s())
ctrl->pin_banks = px30s_pin_banks;
/* Ctrl data re-initialize for some Socs */
if (ctrl->ctrl_data_re_init) {
@@ -3517,6 +3560,13 @@ static struct rockchip_pin_bank px30_pin_banks[] = {
),
};
static struct rockchip_pin_bank px30s_pin_banks[] __maybe_unused = {
PX30S_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, DRV_TYPE_IO_SMIC),
PX30S_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
PX30S_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
PX30S_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
};
static struct rockchip_pin_ctrl px30_pin_ctrl __maybe_unused = {
.pin_banks = px30_pin_banks,
.nr_banks = ARRAY_SIZE(px30_pin_banks),

1
drivers/pinctrl/pinctrl-rockchip.h
View File

@@ -60,6 +60,7 @@ enum rockchip_pin_drv_type {
DRV_TYPE_IO_1V8_ONLY,
DRV_TYPE_IO_1V8_3V0_AUTO,
DRV_TYPE_IO_3V3_ONLY,
DRV_TYPE_IO_SMIC,
DRV_TYPE_MAX
};

5
drivers/power/avs/rockchip-io-domain.c
View File

@@ -28,6 +28,7 @@
#include <linux/regulator/of_regulator.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/rockchip/cpu.h>
#include "../../regulator/internal.h"
#define MAX_SUPPLIES 16
@@ -844,6 +845,10 @@ static int rockchip_iodomain_probe(struct platform_device *pdev)
if (!supply_name)
continue;
/* PX30s pmuio1 not support 1v8 mode switch. */
if (soc_is_px30s() && (!strcmp(supply_name, "pmuio1")))
continue;
reg = devm_regulator_get_optional(iod->dev, supply_name);
if (IS_ERR(reg)) {
ret = PTR_ERR(reg);

19
drivers/soc/rockchip/rockchip-cpuinfo.c
View File

@@ -105,6 +105,23 @@ static struct platform_driver rockchip_cpuinfo_driver = {
},
};
static void px30_init(void)
{
void __iomem *base;
rockchip_soc_id = ROCKCHIP_SOC_PX30;
#define PX30_DDR_GRF_BASE 0xFF630000
#define PX30_DDR_GRF_CON1 0x04
base = ioremap(PX30_DDR_GRF_BASE, SZ_4K);
if (base) {
unsigned int val = readl_relaxed(base + PX30_DDR_GRF_CON1);
if (((val >> 14) & 0x03) == 0x03)
rockchip_soc_id = ROCKCHIP_SOC_PX30S;
iounmap(base);
}
}
static void rv1109_init(void)
{
rockchip_soc_id = ROCKCHIP_SOC_RV1109;
@@ -214,6 +231,8 @@ int __init rockchip_soc_id_init(void)
rk3566_init();
} else if (cpu_is_rk3568()) {
rk3568_init();
} else if (cpu_is_px30()) {
px30_init();
}
return 0;

69
drivers/thermal/rockchip_thermal.c
View File

@@ -23,6 +23,7 @@
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/rockchip/cpu.h>
#include <linux/thermal.h>
#include <linux/mfd/syscon.h>
#include <linux/pinctrl/consumer.h>
@@ -105,6 +106,7 @@ struct chip_tsadc_table {
* @set_tshut_mode: set the hardware-controlled shutdown mode
* @get_trim_code: get the trim code by otp value
* @trim_temp: get trim temp by trim code
* @set_clk_rate: set clock rate
* @table: the chip-specific conversion table
*/
struct rockchip_tsadc_chip {
@@ -135,6 +137,7 @@ struct rockchip_tsadc_chip {
int (*get_trim_code)(struct platform_device *pdev,
int code, int trim_base);
int (*trim_temp)(struct platform_device *pdev);
int (*set_clk_rate)(struct platform_device *pdev);
/* Per-table methods */
struct chip_tsadc_table table;
@@ -241,6 +244,7 @@ struct rockchip_thermal_data {
#define GRF_TSADC_TESTBIT_L 0x0e648
#define GRF_TSADC_TESTBIT_H 0x0e64c
#define PX30_GRF_SOC_CON0 0x0400
#define PX30_GRF_SOC_CON2 0x0408
#define RK1808_BUS_GRF_SOC_CON0 0x0400
@@ -264,6 +268,8 @@ struct rockchip_thermal_data {
#define GRF_TSADC_VCM_EN_H (0x10001 << 7)
#define GRF_CON_TSADC_CH_INV (0x10001 << 1)
#define PX30S_TSADC_TDC_MODE (0x10001 << 4)
#define PX30S_TSADC_TRIM (0xf0007 << 0)
#define MIN_TEMP (-40000)
#define LOWEST_TEMP (-273000)
@@ -899,6 +905,16 @@ static void rk_tsadcv7_initialize(struct regmap *grf, void __iomem *regs,
}
}
static void rk_tsadcv9_initialize(struct regmap *grf, void __iomem *regs,
enum tshut_polarity tshut_polarity)
{
rk_tsadcv2_initialize(grf, regs, tshut_polarity);
if (!IS_ERR(grf)) {
regmap_write(grf, PX30_GRF_SOC_CON0, PX30S_TSADC_TDC_MODE);
regmap_write(grf, PX30_GRF_SOC_CON0, PX30S_TSADC_TRIM);
}
}
static void rk_tsadcv2_irq_ack(void __iomem *regs)
{
u32 val;
@@ -1159,6 +1175,29 @@ static int rk_tsadcv1_trim_temp(struct platform_device *pdev)
return thermal->trim * 500;
}
static int rk_tsadcv1_set_clk_rate(struct platform_device *pdev)
{
struct clk *clk;
int error;
clk = devm_clk_get(&pdev->dev, "tsadc");
if (IS_ERR(clk)) {
error = PTR_ERR(clk);
dev_err(&pdev->dev, "failed to get tsadc clock\n");
return error;
}
error = clk_set_rate(clk, 4000000);
if (error < 0) {
devm_clk_put(&pdev->dev, clk);
dev_err(&pdev->dev,
"failed to set tsadc clk rate to 4000000Hz\n");
return error;
}
devm_clk_put(&pdev->dev, clk);
return 0;
}
static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
.chn_num = 1, /* one channel for tsadc */
@@ -1330,6 +1369,28 @@ static const struct rockchip_tsadc_chip px30_tsadc_data = {
},
};
static const struct rockchip_tsadc_chip px30s_tsadc_data = {
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
.chn_num = 2, /* 1 channels for tsadc */
.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
.tshut_temp = 95000,
.initialize = rk_tsadcv9_initialize,
.irq_ack = rk_tsadcv3_irq_ack,
.control = rk_tsadcv2_control,
.get_temp = rk_tsadcv2_get_temp,
.set_alarm_temp = rk_tsadcv2_alarm_temp,
.set_tshut_temp = rk_tsadcv2_tshut_temp,
.set_tshut_mode = rk_tsadcv2_tshut_mode,
.set_clk_rate = rk_tsadcv1_set_clk_rate,
.table = {
.kNum = 2699,
.bNum = 2796,
.data_mask = TSADCV2_DATA_MASK,
.mode = ADC_INCREMENT,
},
};
static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
.chn_num = 1, /* one channels for tsadc */
@@ -1470,6 +1531,9 @@ static const struct of_device_id of_rockchip_thermal_match[] = {
{ .compatible = "rockchip,px30-tsadc",
.data = (void *)&px30_tsadc_data,
},
{ .compatible = "rockchip,px30s-tsadc",
.data = (void *)&px30s_tsadc_data,
},
#endif
#ifdef CONFIG_CPU_RK1808
{
@@ -1828,6 +1892,8 @@ static int rockchip_thermal_probe(struct platform_device *pdev)
thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
if (!thermal->chip)
return -EINVAL;
if (soc_is_px30s())
thermal->chip = &px30s_tsadc_data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
thermal->regs = devm_ioremap_resource(&pdev->dev, res);
@@ -1853,6 +1919,9 @@ static int rockchip_thermal_probe(struct platform_device *pdev)
}
platform_set_drvdata(pdev, thermal);
if (thermal->chip->set_clk_rate)
thermal->chip->set_clk_rate(pdev);
thermal->chip->control(thermal->regs, false);
rockchip_thermal_reset_controller(thermal->reset);

3
include/dt-bindings/clock/px30-cru.h
View File

@@ -390,4 +390,7 @@
#define SRST_GRF_P 186
#define SRST_I2S0_RX 191
#define SRST_I2S0_RX_S 128
#define SRST_DCF_P_S 191
#endif

8
include/dt-bindings/memory/px30-dram.h
View File

@@ -129,4 +129,12 @@
#define PHY_DDR4_LPDDR3_2_RON_RTT_21ohm (30)
#define PHY_DDR4_LPDDR3_2_RON_RTT_20ohm (31)
#define LP4_VDDQ_2_5 (0)
#define LP4_VDDQ_3 (1)
#define LP4X_VDDQ_0_6 (0)
#define LP4X_VDDQ_0_5 (1)
#define IGNORE_THIS (0)
#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_PX30_H*/

19
include/linux/rockchip/cpu.h
View File

@@ -18,6 +18,7 @@
#define ROCKCHIP_CPU_MASK 0xffff0000
#define ROCKCHIP_CPU_SHIFT 16
#define ROCKCHIP_CPU_PX30 0x33260000
#define ROCKCHIP_CPU_RV1109 0x11090000
#define ROCKCHIP_CPU_RV1126 0x11260000
#define ROCKCHIP_CPU_RK312X 0x31260000
@@ -81,6 +82,20 @@ static inline int rockchip_soc_id_init(void)
#endif
#ifdef CONFIG_CPU_PX30
static inline bool cpu_is_px30(void)
{
if (rockchip_soc_id)
return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_PX30;
return of_machine_is_compatible("rockchip,px30") ||
of_machine_is_compatible("rockchip,px30s") ||
of_machine_is_compatible("rockchip,rk3326") ||
of_machine_is_compatible("rockchip,rk3326s");
}
#else
static inline bool cpu_is_px30(void) { return false; }
#endif
#if defined(CONFIG_CPU_RV1126) || defined(CONFIG_CPU_RV1109)
static inline bool cpu_is_rv1109(void)
{
@@ -158,6 +173,8 @@ static inline bool cpu_is_rk3568(void) { return false; }
#endif
#define ROCKCHIP_SOC_MASK (ROCKCHIP_CPU_MASK | 0xff)
#define ROCKCHIP_SOC_PX30 (ROCKCHIP_CPU_PX30 | 0x00)
#define ROCKCHIP_SOC_PX30S (ROCKCHIP_CPU_PX30 | 0x01)
#define ROCKCHIP_SOC_RV1109 (ROCKCHIP_CPU_RV1109 | 0x00)
#define ROCKCHIP_SOC_RV1126 (ROCKCHIP_CPU_RV1126 | 0x00)
#define ROCKCHIP_SOC_RK3126 (ROCKCHIP_CPU_RK312X | 0x00)
@@ -179,6 +196,8 @@ static inline bool soc_is_##id(void) \
return of_machine_is_compatible("rockchip,"#id); \
}
ROCKCHIP_SOC(px30, PX30)
ROCKCHIP_SOC(px30s, PX30S)
ROCKCHIP_SOC(rv1109, RV1109)
ROCKCHIP_SOC(rv1126, RV1126)
ROCKCHIP_SOC(rk3126, RK3126)