From 22e1c3dbb7ba5a6781ad37067355611753832bc7 Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Wed, 6 Jan 2021 12:15:03 +0000 Subject: [PATCH] drm/bridge: analogix_dp: Fix voltage_swing/pre_emphasis level calculation Fixes: d7ad116fb30d1 ("drm/rockchip: analogix_dp: Add support for rk3568") Signed-off-by: Wyon Bi Change-Id: I6da4a8c0c4b5486bac6bb054aee6535118e81f60 --- drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c index 0d8e0a03ea2e..04195f798316 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c @@ -716,10 +716,10 @@ void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp) u8 training_lane = dp->link_train.training_lane[lane]; u8 vs, pe; - vs = (training_lane >> DP_TRAIN_VOLTAGE_SWING_SHIFT) & - DP_TRAIN_VOLTAGE_SWING_MASK; - pe = (training_lane >> DP_TRAIN_PRE_EMPHASIS_SHIFT) & - DP_TRAIN_PRE_EMPHASIS_MASK; + vs = (training_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >> + DP_TRAIN_VOLTAGE_SWING_SHIFT; + pe = (training_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >> + DP_TRAIN_PRE_EMPHASIS_SHIFT; phy_cfg.dp.voltage[lane] = vs; phy_cfg.dp.pre[lane] = pe; }