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arm64: Save and restore OSDLR_EL1 across suspend/resume

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commit 827a108e35 upstream.

When the CPU comes out of suspend, the firmware may have modified the OS
Double Lock Register. Save it in an unused slot of cpu_suspend_ctx, and
restore it on resume.

Cc: <stable@vger.kernel.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Jean-Philippe Brucker
2019-04-08 18:17:19 +01:00
committed by Greg Kroah-Hartman
parent ef27496f41
commit 235aeafb93
1 changed files with 14 additions and 12 deletions
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26
arch/arm64/mm/proc.S
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@@ -64,17 +64,18 @@ ENTRY(cpu_do_suspend)
mrs x2, tpidr_el0 mrs x2, tpidr_el0
mrs x3, tpidrro_el0 mrs x3, tpidrro_el0
mrs x4, contextidr_el1 mrs x4, contextidr_el1
mrs x5, cpacr_el1 mrs x5, osdlr_el1
mrs x6, tcr_el1 mrs x6, cpacr_el1
mrs x7, vbar_el1 mrs x7, tcr_el1
mrs x8, mdscr_el1 mrs x8, vbar_el1
mrs x9, oslsr_el1 mrs x9, mdscr_el1
mrs x10, sctlr_el1 mrs x10, oslsr_el1
mrs x11, sctlr_el1
stp x2, x3, [x0] stp x2, x3, [x0]
stp x4, xzr, [x0, #16] stp x4, x5, [x0, #16]
stp x5, x6, [x0, #32] stp x6, x7, [x0, #32]
stp x7, x8, [x0, #48] stp x8, x9, [x0, #48]
stp x9, x10, [x0, #64] stp x10, x11, [x0, #64]
ret ret
ENDPROC(cpu_do_suspend) ENDPROC(cpu_do_suspend)
@@ -96,8 +97,8 @@ ENTRY(cpu_do_resume)
msr cpacr_el1, x6 msr cpacr_el1, x6
/* Don't change t0sz here, mask those bits when restoring */ /* Don't change t0sz here, mask those bits when restoring */
mrs x5, tcr_el1 mrs x7, tcr_el1
bfi x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
msr tcr_el1, x8 msr tcr_el1, x8
msr vbar_el1, x9 msr vbar_el1, x9
@@ -115,6 +116,7 @@ ENTRY(cpu_do_resume)
/* /*
* Restore oslsr_el1 by writing oslar_el1 * Restore oslsr_el1 by writing oslar_el1
*/ */
msr osdlr_el1, x5
ubfx x11, x11, #1, #1 ubfx x11, x11, #1, #1
msr oslar_el1, x11 msr oslar_el1, x11
reset_pmuserenr_el0 x0 // Disable PMU access from EL0 reset_pmuserenr_el0 x0 // Disable PMU access from EL0