From 23f71386321a752d6deb2b341f25b5e509d1bdc2 Mon Sep 17 00:00:00 2001 From: Jihong Sui Date: Thu, 10 Jan 2019 20:48:47 +0800 Subject: [PATCH] deinterlace: change holdline default value to 8 [1/1] PD#SWPL-3384 Problem: DI post holdline setting is not map with video Solution: change holdline to 8 Verify: verified by gxl Change-Id: Ia352604086cefb4c69d5dd268d12741c4cf4f173 Signed-off-by: Jihong Sui --- drivers/amlogic/media/deinterlace/deinterlace.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/amlogic/media/deinterlace/deinterlace.c b/drivers/amlogic/media/deinterlace/deinterlace.c index 79fb623d9347..4a0afc00e6e7 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace.c +++ b/drivers/amlogic/media/deinterlace/deinterlace.c @@ -263,7 +263,7 @@ static long same_field_bot_count; * 1, keep 4 buffers in pre_ready_list for checking; */ -static int post_hold_line = 17;/* for m8 1080i/50 output */ +static int post_hold_line = 8; /*2019-01-10: from VLSI feijun from 17 to 8*/ static int post_urgent = 1; /*pre process speed debug */ @@ -7405,6 +7405,7 @@ static void set_di_flag(void) post_hold_line = (is_meson_g12a_cpu() || is_meson_g12b_cpu())?10:17; } else { + post_hold_line = 8; /*2019-01-10: from VLSI feijun*/ mcpre_en = false; pulldown_enable = false; di_pre_rdma_enable = false;