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x86/cpu: Sanitize FAM6_ATOM naming
commit f2c4db1bd8 upstream.
Going primarily by:
https://en.wikipedia.org/wiki/List_of_Intel_Atom_microprocessors
with additional information gleaned from other related pages; notably:
- Bonnell shrink was called Saltwell
- Moorefield is the Merriefield refresh which makes it Airmont
The general naming scheme is: FAM6_ATOM_UARCH_SOCTYPE
for i in `git grep -l FAM6_ATOM` ; do
sed -i -e 's/ATOM_PINEVIEW/ATOM_BONNELL/g' \
-e 's/ATOM_LINCROFT/ATOM_BONNELL_MID/' \
-e 's/ATOM_PENWELL/ATOM_SALTWELL_MID/g' \
-e 's/ATOM_CLOVERVIEW/ATOM_SALTWELL_TABLET/g' \
-e 's/ATOM_CEDARVIEW/ATOM_SALTWELL/g' \
-e 's/ATOM_SILVERMONT1/ATOM_SILVERMONT/g' \
-e 's/ATOM_SILVERMONT2/ATOM_SILVERMONT_X/g' \
-e 's/ATOM_MERRIFIELD/ATOM_SILVERMONT_MID/g' \
-e 's/ATOM_MOOREFIELD/ATOM_AIRMONT_MID/g' \
-e 's/ATOM_DENVERTON/ATOM_GOLDMONT_X/g' \
-e 's/ATOM_GEMINI_LAKE/ATOM_GOLDMONT_PLUS/g' ${i}
done
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: dave.hansen@linux.intel.com
Cc: len.brown@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
[bwh: Backported to 4.4:
- Drop changes to CPU IDs that weren't already included
- Adjust context]
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
2329f765b5
commit
2422db18b6
@@ -50,19 +50,23 @@
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/* "Small Core" Processors (Atom) */
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#define INTEL_FAM6_ATOM_PINEVIEW 0x1C
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#define INTEL_FAM6_ATOM_LINCROFT 0x26
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#define INTEL_FAM6_ATOM_PENWELL 0x27
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#define INTEL_FAM6_ATOM_CLOVERVIEW 0x35
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#define INTEL_FAM6_ATOM_CEDARVIEW 0x36
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#define INTEL_FAM6_ATOM_SILVERMONT1 0x37 /* BayTrail/BYT / Valleyview */
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#define INTEL_FAM6_ATOM_SILVERMONT2 0x4D /* Avaton/Rangely */
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#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* CherryTrail / Braswell */
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#define INTEL_FAM6_ATOM_MERRIFIELD 0x4A /* Tangier */
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#define INTEL_FAM6_ATOM_MOOREFIELD 0x5A /* Annidale */
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#define INTEL_FAM6_ATOM_GOLDMONT 0x5C
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#define INTEL_FAM6_ATOM_DENVERTON 0x5F /* Goldmont Microserver */
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#define INTEL_FAM6_ATOM_GEMINI_LAKE 0x7A
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#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
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#define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */
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#define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */
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#define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */
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#define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */
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#define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */
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#define INTEL_FAM6_ATOM_SILVERMONT_X 0x4D /* Avaton, Rangely */
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#define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */
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#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */
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#define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */
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#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
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#define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
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#define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */
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/* Xeon Phi */
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@@ -848,11 +848,11 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
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}
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static const __initconst struct x86_cpu_id cpu_no_speculation[] = {
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SALTWELL, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SALTWELL_TABLET, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_BONNELL_MID, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SALTWELL_MID, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_BONNELL, X86_FEATURE_ANY },
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{ X86_VENDOR_CENTAUR, 5 },
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{ X86_VENDOR_INTEL, 5 },
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{ X86_VENDOR_NSC, 5 },
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@@ -867,10 +867,10 @@ static const __initconst struct x86_cpu_id cpu_no_meltdown[] = {
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/* Only list CPUs which speculate but are non susceptible to SSB */
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static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = {
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MERRIFIELD },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_X },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_MID },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_CORE_YONAH },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM },
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@@ -883,14 +883,14 @@ static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = {
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static const __initconst struct x86_cpu_id cpu_no_l1tf[] = {
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/* in addition to cpu_no_speculation */
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_X },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MERRIFIELD },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MOOREFIELD },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_MID },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT_MID },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_DENVERTON },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GEMINI_LAKE },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_X },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_PLUS },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM },
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{}
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