From 24d23869975aeda60cbc22703fc4ca1592463977 Mon Sep 17 00:00:00 2001 From: YouMin Chen Date: Mon, 5 Feb 2018 10:54:50 +0800 Subject: [PATCH] clk: rockchip: px30: Add SCLK_DDRCLK for dmc Change-Id: I03d6c18829f8895c28bbaef883e187304c48f9aa Signed-off-by: YouMin Chen Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-px30.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c index 55d4735eec67..24850865a613 100644 --- a/drivers/clk/rockchip/clk-px30.c +++ b/drivers/clk/rockchip/clk-px30.c @@ -326,8 +326,9 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = { PX30_CLKGATE_CON(0), 7, GFLAGS), GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(0), 13, GFLAGS), - COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, CLK_IGNORE_UNUSED, - PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), + COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, + CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(2), 7, 1, 0, 3, + ROCKCHIP_DDRCLK_SIP_V2), COMPOSITE_NOGATE(0, "clk_ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS), FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,