From 24ea6649adbb2c8e66b481cab90a2e9e9fcffa21 Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@rock-chips.com>
Date: Thu, 17 Aug 2023 09:26:00 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3562-evb1-lp4x-v10: Change clkin div
 to 5 for aclk vo

The dclk vop is 132MHz, the aclk vop can be reduced appropriately.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I80d060fd90e013aaa1eea4d94868731e3cf02ffb
---
 .../boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi      | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi
index 7fdb0557edda..44f2ff713dde 100644
--- a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi
@@ -179,6 +179,18 @@
 	};
 };
 
+&bus_soc {
+	rockchip,soc-bus-table = <0 0x00a000a8 0x7001>,
+				 <1 0x00a000a8 0x7c39>,
+				 <2 0x00a000a8 0x7c39>,
+				 <3 0x00a000a8 0x7c39>,
+				 <4 0x00a000a5 0xb007>,
+				 <5 0x00a000a8 0x7034>,
+				 <6 0x00a000a8 0x7034>,
+				 <7 0x00a000a8 0x7034>,
+				 <8 0x00a000a8 0x7001>;
+};
+
 &gmac0 {
 	/* Use rgmii-rxid mode to disable rx delay inside Soc */
 	phy-mode = "rgmii-rxid";