From 2598d85d44d799d366ee772ab49302d24610af12 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Mon, 6 Jun 2022 11:44:20 +0800 Subject: [PATCH] MALI: bifrost: Add missing error code in kbase_devfreq_opp_helper() Fixes: eb26be047e76 ("MALI: bifrost: Set intermediate rate before change read margin") Signed-off-by: Finley Xiao Change-Id: Id4df3e3b990762bc737d1b78f44e95fa00d12aff --- drivers/gpu/arm/bifrost/backend/gpu/mali_kbase_devfreq.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/arm/bifrost/backend/gpu/mali_kbase_devfreq.c b/drivers/gpu/arm/bifrost/backend/gpu/mali_kbase_devfreq.c index ab1b2fb1d8e8..0879c03c8436 100644 --- a/drivers/gpu/arm/bifrost/backend/gpu/mali_kbase_devfreq.c +++ b/drivers/gpu/arm/bifrost/backend/gpu/mali_kbase_devfreq.c @@ -182,7 +182,8 @@ int kbase_devfreq_opp_helper(struct dev_pm_set_opp_data *data) } rockchip_set_read_margin(dev, opp_info, target_rm, is_set_rm); if (is_set_clk && clk_set_rate(clk, new_freq)) { - dev_err(dev, "failed to set clk rate: %d\n", ret); + ret = -EINVAL; + dev_err(dev, "failed to set clk rate\n"); goto restore_rm; } /* Scaling down? Scale voltage after frequency */ @@ -191,7 +192,8 @@ int kbase_devfreq_opp_helper(struct dev_pm_set_opp_data *data) new_freq, false, is_set_clk); rockchip_set_read_margin(dev, opp_info, target_rm, is_set_rm); if (is_set_clk && clk_set_rate(clk, new_freq)) { - dev_err(dev, "failed to set clk rate: %d\n", ret); + ret = -EINVAL; + dev_err(dev, "failed to set clk rate\n"); goto restore_rm; } ret = regulator_set_voltage(vdd_reg, new_supply_vdd->u_volt,