From 25b712aa8f4287f80a520bcb7d815873d9ab86c1 Mon Sep 17 00:00:00 2001
From: Huang zhibao <hzb@rock-chips.com>
Date: Tue, 2 Feb 2021 10:17:16 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3568-nvr: add pcie3.0 support

Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: I04d6fce4a0a858f6e6738d3c644292350bd7e276
---
 .../dts/rockchip/rk3568-nvr-demo-v10.dtsi     | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nvr-demo-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-nvr-demo-v10.dtsi
index c953374f473f..12d154cd128e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-nvr-demo-v10.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nvr-demo-v10.dtsi
@@ -53,6 +53,17 @@
 		vin-supply = <&vcc3v3_sys>;
 	};
 
+	pcie30_3v3: gpio-regulator {
+		compatible = "regulator-gpio";
+		regulator-name = "pcie30_3v3";
+		regulator-min-microvolt = <0100000>;
+		regulator-max-microvolt = <3300000>;
+		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		gpios-states = <0x1>;
+		states = <0100000 0x0
+			  3300000 0x1>;
+	};
+
 	pcie30_avdd0v9: pcie30-avdd0v9 {
 		compatible = "regulator-fixed";
 		regulator-name = "pcie30_avdd0v9";
@@ -199,6 +210,22 @@
 	};
 };
 
+&pcie30phy {
+	status = "okay";
+};
+
+&pcie3x1 {
+	reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&pcie30_3v3>;
+	status = "okay";
+};
+
+&pcie3x2 {
+	reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&pcie30_3v3>;
+	status = "okay";
+};
+
 &pwm15 {
 	compatible = "rockchip,remotectl-pwm";
 	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;