From 25c456719d40272e5da224021cdddc76bdc48840 Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Tue, 20 Feb 2024 15:14:57 +0800 Subject: [PATCH] clk: rockchip: rv1106: optimize calibrate step for cru pvtpll The frequency of pvtpll may unstable when calibrate, if the step is too small, it will stride a too big length and adjust back again, that is bad. Signed-off-by: Liang Chen Change-Id: I96227b37cde45ae86df68777da8f32467f8926e6 --- drivers/clk/rockchip/clk-rv1106.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rv1106.c b/drivers/clk/rockchip/clk-rv1106.c index f61cbbf2e81d..84d0099ddcab 100644 --- a/drivers/clk/rockchip/clk-rv1106.c +++ b/drivers/clk/rockchip/clk-rv1106.c @@ -1007,12 +1007,16 @@ static void _cru_pvtpll_calibrate(int count_offset, int length_offset, int targe writel_relaxed(val, rv1106_cru_base + length_offset); usleep_range(2000, 2100); rate1 = readl_relaxed(rv1106_cru_base + count_offset); - if ((rate1 < target_rate) || (rate1 >= rate0)) + if (rate1 < target_rate) return; if (abs(rate1 - target_rate) < (target_rate >> 5)) return; - step = rate0 - rate1; + if (rate1 < rate0) + step = rate0 - rate1; + else + step = 5; + step = max_t(unsigned int, step, 5); delta = rate1 - target_rate; length += delta / step; val = HIWORD_UPDATE(length, PVTPLL_LENGTH_SEL_MASK, PVTPLL_LENGTH_SEL_SHIFT);