From 25cfc3a02034d8b67d9f0730001bff5bd53efa06 Mon Sep 17 00:00:00 2001
From: David Wu <david.wu@rock-chips.com>
Date: Mon, 22 Jan 2018 22:50:10 +0800
Subject: [PATCH] arm64: dts: rockchip: Enable gmac at px30*.dts level

Change-Id: I3d6b4cfc8daa51f52f8fadddcad0cde8b098c53e
Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 .../boot/dts/rockchip/px30-evb-ddr3-v10.dts      | 16 ++++++++++++++++
 .../boot/dts/rockchip/px30-evb-ddr4-v10.dts      | 16 ++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dts b/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dts
index 98d3edf9a991..8cee7cf6686c 100644
--- a/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dts
@@ -109,6 +109,13 @@
 		reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */
 	};
 
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
 	wireless-wlan {
 		compatible = "wlan-platdata";
 		wifi_chip_type = "AP6210";
@@ -324,6 +331,15 @@
 	status = "disabled";
 };
 
+&gmac {
+	phy-supply = <&vcc_phy>;
+	clock_in_out = "output";
+	snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 50000 50000>;
+	status = "okay";
+};
+
 &mipi_dphy {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/rockchip/px30-evb-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/px30-evb-ddr4-v10.dts
index 13737b6d87d3..c031ce5c25fb 100644
--- a/arch/arm64/boot/dts/rockchip/px30-evb-ddr4-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-evb-ddr4-v10.dts
@@ -49,6 +49,13 @@
 			248 249 250 251 252 253 254 255>;
 		default-brightness-level = <200>;
 	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
 };
 
 &display_subsystem {
@@ -178,6 +185,15 @@
 	status = "disabled";
 };
 
+&gmac {
+	phy-supply = <&vcc_phy>;
+	clock_in_out = "output";
+	snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 50000 50000>;
+	status = "okay";
+};
+
 &mipi_dphy {
 	status = "okay";
 };