From b3ea30f4d4e196dcd677ab8c3e6f2433a2e04c87 Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Wed, 15 May 2024 18:57:23 +0800 Subject: [PATCH 1/9] drm/rockchip: dw-dp: select encoder by the correct crtc Change-Id: If459d759403fdbeddde9ce121de292d72c7b0541 Signed-off-by: Zhang Yubing --- drivers/gpu/drm/rockchip/dw-dp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw-dp.c b/drivers/gpu/drm/rockchip/dw-dp.c index 6610b76799dd..7ece490e33fa 100644 --- a/drivers/gpu/drm/rockchip/dw-dp.c +++ b/drivers/gpu/drm/rockchip/dw-dp.c @@ -3329,7 +3329,8 @@ static void dw_dp_mst_assigned_encoder(struct dw_dp *dp, struct drm_atomic_state if (!connector->state->crtc && new_con_state->crtc) { availble_encoders = encoder_mask ^ connector->possible_encoders; for (i = 0; i < dp->mst_port_num; i++) { - if (drm_encoder_crtc_ok(&dp->mst_enc[i].encoder, crtc) && + if (drm_encoder_crtc_ok(&dp->mst_enc[i].encoder, + new_con_state->crtc) && (availble_encoders & drm_encoder_mask(&dp->mst_enc[i].encoder))) { mst_conn->mst_enc = &dp->mst_enc[i]; From 83ed0e999d4e4ebbfaec659e5af993d812001b17 Mon Sep 17 00:00:00 2001 From: Wang Panzhenzhuan Date: Mon, 27 May 2024 19:12:50 +0800 Subject: [PATCH 2/9] media: i2c: ov16885: fix vflip ghost issue 1. fix vflip ghost issue. 2. add write/read reg failed log. Signed-off-by: Wang Panzhenzhuan Change-Id: I83d6a92f163c8f504b71e4d38b063c7bb5af3550 --- drivers/media/i2c/ov16885.c | 57 +++++++++++++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 6 deletions(-) diff --git a/drivers/media/i2c/ov16885.c b/drivers/media/i2c/ov16885.c index f2f82c535fd5..46fd1840f51d 100644 --- a/drivers/media/i2c/ov16885.c +++ b/drivers/media/i2c/ov16885.c @@ -5,6 +5,9 @@ * Copyright (C) 2023 Rockchip Electronics Co., Ltd. * * V0.0X01.0X00 first version. + * V0.0X01.0X01 + * 1. fix vflip ghost issue. + * 2. add write/read reg failed log. * */ //#define DEBUG @@ -27,7 +30,7 @@ #include #include -#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00) +#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01) #define OV16885_MAJOR_I2C_ADDR 0x36 #define OV16885_MINOR_I2C_ADDR 0x10 @@ -70,6 +73,8 @@ #define OV16885_SOFTWARE_RESET_REG 0x0103 #define OV16885_REG_ISP_X_WIN 0x3810 +#define OV16885_REG_ISP_Y_WIN 0x3812 +#define OV16885_REG_SYNC_FIF0_CTRL 0x4500 #define OV16885_GROUP_UPDATE_ADDRESS 0x3208 #define OV16885_GROUP_UPDATE_START_DATA 0x00 @@ -958,8 +963,11 @@ static int ov16885_write_reg(struct i2c_client *client, u16 reg, while (val_i < 4) buf[buf_i++] = val_p[val_i++]; - if (i2c_master_send(client, buf, len + 2) != len + 2) + if (i2c_master_send(client, buf, len + 2) != len + 2) { + dev_err(&client->dev, + "write reg(0x%x val:0x%x)!\n", reg, val); return -EIO; + } return 0; } @@ -1005,8 +1013,11 @@ static int ov16885_read_reg(struct i2c_client *client, u16 reg, msgs[1].buf = &data_be_p[4 - len]; ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); - if (ret != ARRAY_SIZE(msgs)) + if (ret != ARRAY_SIZE(msgs)) { + dev_err(&client->dev, + "read reg(0x%x val:0x%x) failed !\n", reg, *val); return -EIO; + } *val = be32_to_cpu(data_be); @@ -1717,7 +1728,7 @@ static int ov16885_set_ctrl(struct v4l2_ctrl *ctrl) struct i2c_client *client = ov16885->client; s64 max; int ret = 0; - u32 val = 0, x_win = 0; + u32 val = 0, x_win = 0, y_win = 0, sync_ctrl = 0; /* Propagate change of current control to all related controls */ switch (ctrl->id) { @@ -1801,12 +1812,46 @@ static int ov16885_set_ctrl(struct v4l2_ctrl *ctrl) OV16885_REG_VALUE_08BIT, &val); if (ctrl->val) - val |= FLIP_BIT_MASK; + val |= (FLIP_BIT_MASK | BIT(6)); else - val &= ~FLIP_BIT_MASK; + val &= ~(FLIP_BIT_MASK | BIT(6)); + + ret |= ov16885_read_reg(ov16885->client, OV16885_REG_ISP_Y_WIN, + OV16885_REG_VALUE_16BIT, + &y_win); + + if ((y_win == 0x0008) && (ctrl->val)) { + y_win = 0x0009; + sync_ctrl = 0x80; + } else if ((y_win == 0x0009) && (!(ctrl->val))) { + y_win = 0x0008; + sync_ctrl = 0x00; + } + + ret |= ov16885_write_reg(ov16885->client, + OV16885_GROUP_UPDATE_ADDRESS, + OV16885_REG_VALUE_08BIT, + OV16885_GROUP_UPDATE_START_DATA); + ret |= ov16885_write_reg(ov16885->client, OV16885_FLIP_REG, OV16885_REG_VALUE_08BIT, val); + ret |= ov16885_write_reg(ov16885->client, OV16885_REG_ISP_Y_WIN, + OV16885_REG_VALUE_16BIT, + y_win); + ret |= ov16885_write_reg(ov16885->client, OV16885_REG_SYNC_FIF0_CTRL, + OV16885_REG_VALUE_08BIT, + sync_ctrl); + + ret |= ov16885_write_reg(ov16885->client, + OV16885_GROUP_UPDATE_ADDRESS, + OV16885_REG_VALUE_08BIT, + OV16885_GROUP_UPDATE_END_DATA); + ret |= ov16885_write_reg(ov16885->client, + OV16885_GROUP_UPDATE_ADDRESS, + OV16885_REG_VALUE_08BIT, + OV16885_GROUP_UPDATE_LAUNCH); + break; default: dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", From 39f174d725373c935a943975491be02f424c5501 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Mon, 29 Jan 2024 10:03:38 +0800 Subject: [PATCH 3/9] arm64: dts: rockchip: rk3588s: Change cpu low temp min vlot to 800mV Signed-off-by: Finley Xiao Change-Id: I5fa1f5a587e90495176a14cf68956af6aa0c63be --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index d049f3875b8c..7319e94ecc15 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -706,7 +706,7 @@ rockchip,temp-hysteresis = <5000>; rockchip,low-temp = <10000>; - rockchip,low-temp-min-volt = <750000>; + rockchip,low-temp-min-volt = <800000>; rockchip,high-temp = <85000>; rockchip,high-temp-max-freq = <1608000>; @@ -971,7 +971,7 @@ rockchip,temp-hysteresis = <5000>; rockchip,low-temp = <10000>; - rockchip,low-temp-min-volt = <750000>; + rockchip,low-temp-min-volt = <800000>; rockchip,high-temp = <85000>; rockchip,high-temp-max-freq = <2208000>; @@ -1304,7 +1304,7 @@ rockchip,temp-hysteresis = <5000>; rockchip,low-temp = <10000>; - rockchip,low-temp-min-volt = <750000>; + rockchip,low-temp-min-volt = <800000>; rockchip,high-temp = <85000>; rockchip,high-temp-max-freq = <2208000>; From 6d64f4c2d4a3f0a22c5dfb2dc59837a5e2251310 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 2 Feb 2024 11:12:22 +0800 Subject: [PATCH 4/9] arm64: dts: rockchip: rk3588s: Change low temp to 15000mC Signed-off-by: Finley Xiao Change-Id: I6cf7d8911944ccc135f0dfa669f0c73185cc2521 --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 7319e94ecc15..6d42de7248fa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -705,7 +705,7 @@ rockchip,reboot-freq = <1416000>; /* KHz */ rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <10000>; + rockchip,low-temp = <15000>; rockchip,low-temp-min-volt = <800000>; rockchip,high-temp = <85000>; rockchip,high-temp-max-freq = <1608000>; @@ -970,7 +970,7 @@ rockchip,reboot-freq = <1800000>; /* KHz */ rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <10000>; + rockchip,low-temp = <15000>; rockchip,low-temp-min-volt = <800000>; rockchip,high-temp = <85000>; rockchip,high-temp-max-freq = <2208000>; @@ -1303,7 +1303,7 @@ rockchip,reboot-freq = <1800000>; /* KHz */ rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <10000>; + rockchip,low-temp = <15000>; rockchip,low-temp-min-volt = <800000>; rockchip,high-temp = <85000>; rockchip,high-temp-max-freq = <2208000>; @@ -1769,7 +1769,7 @@ 58 254 3 >; rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <10000>; + rockchip,low-temp = <15000>; rockchip,low-temp-min-volt = <750000>; /* RK3588 dmc OPPs */ @@ -2432,7 +2432,7 @@ intermediate-threshold-freq = <400000>; /* KHz */ rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <10000>; + rockchip,low-temp = <15000>; rockchip,low-temp-min-volt = <750000>; rockchip,high-temp = <85000>; rockchip,high-temp-max-freq = <800000>; @@ -3525,7 +3525,7 @@ rockchip,init-freq = <1000000>; /* KHz */ rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <10000>; + rockchip,low-temp = <15000>; rockchip,low-temp-min-volt = <750000>; rockchip,high-temp = <85000>; rockchip,high-temp-max-freq = <800000>; From 655b972bccc9dc75f096a8f7fc7d1c1521d516b8 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 1 Feb 2024 21:15:19 +0800 Subject: [PATCH 5/9] arm64: dts: rockchip: rk3588-rk806: Change cpu init volt to 800mV Signed-off-by: Finley Xiao Change-Id: I7687f1f9540033f318098efef52c9db6806651da --- arch/arm64/boot/dts/rockchip/rk3588-rk806-dual.dtsi | 6 ++++++ arch/arm64/boot/dts/rockchip/rk3588-rk806-single.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3588s-rk806-dual.dtsi | 6 ++++++ 3 files changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rk806-dual.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rk806-dual.dtsi index 505676f77a48..49ba5baf1a76 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rk806-dual.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-rk806-dual.dtsi @@ -532,6 +532,7 @@ vdd_cpu_big1_s0: DCDC_REG1 { regulator-always-on; regulator-boot-on; + regulator-init-microvolt = <800000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -544,6 +545,7 @@ vdd_cpu_big0_s0: DCDC_REG2 { regulator-always-on; regulator-boot-on; + regulator-init-microvolt = <800000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -556,6 +558,7 @@ vdd_cpu_lit_s0: DCDC_REG3 { regulator-always-on; regulator-boot-on; + regulator-init-microvolt = <800000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; @@ -580,6 +583,7 @@ vdd_cpu_big1_mem_s0: DCDC_REG5 { regulator-always-on; regulator-boot-on; + regulator-init-microvolt = <800000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -593,6 +597,7 @@ vdd_cpu_big0_mem_s0: DCDC_REG6 { regulator-always-on; regulator-boot-on; + regulator-init-microvolt = <800000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -617,6 +622,7 @@ vdd_cpu_lit_mem_s0: DCDC_REG8 { regulator-always-on; regulator-boot-on; + regulator-init-microvolt = <800000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rk806-single.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rk806-single.dtsi index fa86b4ada299..a56f572c61e5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rk806-single.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-rk806-single.dtsi @@ -165,6 +165,7 @@ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: DCDC_REG2 { regulator-always-on; regulator-boot-on; + regulator-init-microvolt = <800000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rk806-dual.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-rk806-dual.dtsi index a7a0c0f28645..9fe6af59ddc7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rk806-dual.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rk806-dual.dtsi @@ -531,6 +531,7 @@ vdd_cpu_big1_s0: DCDC_REG1 { regulator-always-on; regulator-boot-on; + regulator-init-microvolt = <800000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -543,6 +544,7 @@ vdd_cpu_big0_s0: DCDC_REG2 { regulator-always-on; regulator-boot-on; + regulator-init-microvolt = <800000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -555,6 +557,7 @@ vdd_cpu_lit_s0: DCDC_REG3 { regulator-always-on; regulator-boot-on; + regulator-init-microvolt = <800000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; @@ -580,6 +583,7 @@ vdd_cpu_big1_mem_s0: DCDC_REG5 { regulator-always-on; regulator-boot-on; + regulator-init-microvolt = <800000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -593,6 +597,7 @@ vdd_cpu_big0_mem_s0: DCDC_REG6 { regulator-always-on; regulator-boot-on; + regulator-init-microvolt = <800000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -617,6 +622,7 @@ vdd_cpu_lit_mem_s0: DCDC_REG8 { regulator-always-on; regulator-boot-on; + regulator-init-microvolt = <800000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; From c3a7f7cec32498a001231ee6339ab541eb70b056 Mon Sep 17 00:00:00 2001 From: Zorro Liu Date: Thu, 30 May 2024 08:49:19 +0800 Subject: [PATCH 6/9] arm64: dts: rockchip: init rk806 pwrctrl3 output low for rk3576-eink rk3576 ebook have ultra sleep circuit design, set pwrctrl3 output low to improve system stability Type: Function Redmine ID: #N/A Associated modifications: I7ccb27c54ddb8123fafe8fdbc019702caa9b9861 Test: N/A Change-Id: I260e5069fd3b794683105d2ef425864e88b5ba96 Signed-off-by: Zorro Liu --- arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi index 425b3bbe6389..a67fb9b01f25 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi @@ -63,6 +63,9 @@ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; pinctrl-1 = <&rk806_dvs2_pwrdn>; + //for rk3576 have ultra sleep circuit design + pwrctrl3_output = <0>; + /* 2800mv-3500mv */ low_voltage_threshold = <3000>; /* 2700mv-3400mv */ From 4b8f3fe47550d93596aeb04f0441c13e0e18313f Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 30 May 2024 14:28:49 +0800 Subject: [PATCH 7/9] arm64: dts: rockchip: rk3576: Change low temp config for opp table Change-Id: I87569675f1140b756722b9ba818730606f0299cb Signed-off-by: Finley Xiao --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 21c831e4a483..357c6e2518a9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -427,8 +427,8 @@ rockchip,reboot-freq = <1416000>; rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <10000>; - rockchip,low-temp-min-volt = <750000>; + rockchip,low-temp = <15000>; + rockchip,low-temp-min-volt = <800000>; opp-408000000 { opp-hz = /bits/ 64 <408000000>; @@ -545,8 +545,8 @@ rockchip,reboot-freq = <1608000>; rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <10000>; - rockchip,low-temp-min-volt = <750000>; + rockchip,low-temp = <15000>; + rockchip,low-temp-min-volt = <800000>; opp-408000000 { opp-hz = /bits/ 64 <408000000>; @@ -821,7 +821,7 @@ rockchip,early-min-microvolt = <0 750000>; /* */ rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <10000>; + rockchip,low-temp = <15000>; rockchip,low-temp-min-volt = <750000>; rockchip,leakage-voltage-sel = < @@ -2057,7 +2057,7 @@ <&cru PCLK_NPUTOP_ROOT>; rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <10000>; + rockchip,low-temp = <15000>; rockchip,low-temp-min-volt = <750000>; opp-300000000 { @@ -2180,7 +2180,7 @@ rockchip,opp-clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>; rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <10000>; + rockchip,low-temp = <15000>; rockchip,low-temp-min-volt = <750000>; opp-300000000 { @@ -2911,6 +2911,10 @@ rockchip,early-min-microvolt = <750000>; /* vdd_logic */ + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <15000>; + rockchip,low-temp-min-volt = <750000>; + rockchip,init-freq = <702000>; /* KHz */ rockchip,leakage-voltage-sel = < From 915826d69199d56319a028f3eec4e0e03a46263b Mon Sep 17 00:00:00 2001 From: William Wu Date: Wed, 29 May 2024 15:41:17 +0800 Subject: [PATCH 8/9] phy: rockchip: inno-usb2: Clear charger state in host mode Test on RK3576 Tablet Android 14 GKI, when plug in U disk, it will trigger the usb2 phy to do charging detection logic in the following process. 1. Type-C PD controller chip (e.g HUSB311) detect DFP mode; 2. Type-C tcpm call usb_role_switch_set_role() to notify the usb controller to set USB_ROLE_HOST; 3. The usb dwc3 controller driver do dwc3_set_mode() to initialize the controller and phy for host mode; 4. In the __dwc3_set_mode(), it do pm_runtime_get_sync() -> dwc3_runtime_resume() -> dwc3_resume_common() -> dwc3_core_init() -> phy_init(dwc->usb2_generic_phy); 5. In the usb2 phy driver, it do rockchip_usb2phy_init() -> schedule otg_sm_work -> rockchip_chg_detect_work() 6. Detect dcp cable is connected, and call extcon_set_state_sync() to send charger notification with true state. Later, if plug out the U disk and plug in a USB charger, it will fail to send charger notification because its extcon state still in true state. To fix this issue, we need to clear the charger state in the otg_sm_work if it's already in host mode. Signed-off-by: William Wu Change-Id: I6a30429162290927cae3e5f3495f51db61bf15b6 --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 7345cc289193..c1c1a79e54c5 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -1253,6 +1253,10 @@ static void rockchip_usb2phy_otg_sm_work(struct work_struct *work) rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; mutex_unlock(&rport->mutex); rockchip_usb2phy_power_on(rport->phy); + if (extcon_get_state(rphy->edev, cable)) { + extcon_set_state_sync(rphy->edev, cable, false); + cable = EXTCON_NONE; + } return; } else if (rport->vbus_attached) { dev_dbg(&rport->phy->dev, "vbus_attach\n"); From 89b7bdea30f21459fa9661cd26ac9fd59f9da148 Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Tue, 28 May 2024 09:32:38 +0800 Subject: [PATCH 9/9] drm/rockchip: vop2: get correct dclk source when fixup dclk rate For rk3576 and rk3588, vop dclk can be from pll or hdmi phy[except hdmi 2.1(dclk bigger than 597M), the HDMI work at FRL mode], when dclk is from pll, dclk_parent is equal to dclk, we need clk_round_rate() for dclk_parent to check whether can support this mode. 1. GPLL/CPLL/VPLL dclk_parent dclk 2. xin24m clk_hdmiphy_pixel0 dclk Change-Id: Ie5b9a7a5056a6f997ade95ab6af9b6d7ddc10f3b Signed-off-by: Zhang Yubing --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index af3224f713de..5e59371afd04 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -7896,8 +7896,10 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc, drm_connector_list_iter_end(&conn_iter); if (adj_mode->crtc_clock <= VOP2_MAX_DCLK_RATE) { - adj_mode->crtc_clock = rockchip_drm_dclk_round_rate(vop2->version, vp->dclk, - adj_mode->crtc_clock * 1000); + adj_mode->crtc_clock = + rockchip_drm_dclk_round_rate(vop2->version, + vp->dclk_parent ? vp->dclk_parent : vp->dclk, + adj_mode->crtc_clock * 1000); adj_mode->crtc_clock = DIV_ROUND_UP(adj_mode->crtc_clock, 1000); } return true;