From 26d58236a5e4ee47eb13c2dbbac4b0699a313e18 Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@rock-chips.com>
Date: Thu, 17 Aug 2023 09:25:00 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3562-rk817-tablet-v10: Change clkin
 div to 5 for aclk vo

The dclk vop is 70MHz, the aclk vop can be reduced appropriately.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I05f79bb4bade6c8ff6c8014edce448f403bb9ca4
---
 .../boot/dts/rockchip/rk3562-rk817-tablet-v10.dts    | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts
index 4f9edc072df7..281b65104b53 100644
--- a/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts
@@ -209,6 +209,18 @@
 	cpu-supply = <&vdd_cpu>;
 };
 
+&bus_soc {
+	rockchip,soc-bus-table = <0 0x00a000a8 0x7001>,
+				 <1 0x00a000a8 0x7c39>,
+				 <2 0x00a000a8 0x7c39>,
+				 <3 0x00a000a8 0x7c39>,
+				 <4 0x00a000a5 0xb007>,
+				 <5 0x00a000a8 0x7034>,
+				 <6 0x00a000a8 0x7034>,
+				 <7 0x00a000a8 0x7034>,
+				 <8 0x00a000a8 0x7001>;
+};
+
 &dfi {
 	status = "okay";
 };