diff --git a/arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10.dtsi index 2de69e2c280c..65849ed3467c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10.dtsi @@ -55,27 +55,28 @@ status = "okay"; }; -&csi_dphy { +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy2 { status = "okay"; - /*lane-mode: - * index0: 4 means full mode, 2 means split mode - * index1: 1 means using lane0/1, 2 means using lane2/3 - * attention: if lane-mode is not set, default mode is full mode, - * full mode and split mode are mutually exclusive - * eg: rockchip,lane-mode = <2 1>, means using split mode, and using lane0/1 + /* + * dphy2 only used for split mode, + * can be used concurrently with dphy1 + * full mode and split mode are mutually exclusive */ - rockchip,lane-mode = <2 2>; - ports { #address-cells = <1>; #size-cells = <0>; + port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; - mipi_in_ucam1: endpoint@1 { + dphy2_in: endpoint@1 { reg = <1>; remote-endpoint = <&ov02k10_out>; data-lanes = <1 2>; @@ -87,7 +88,7 @@ #address-cells = <1>; #size-cells = <0>; - csidphy_out: endpoint@1 { + dphy2_out: endpoint@1 { reg = <1>; remote-endpoint = <&mipi_csi2_input>; }; @@ -209,7 +210,7 @@ rockchip,camera-module-lens-name = "CHT842-MD"; port { ov02k10_out: endpoint { - remote-endpoint = <&mipi_in_ucam1>; + remote-endpoint = <&dphy2_in>; data-lanes = <1 2>; }; }; @@ -234,7 +235,7 @@ mipi_csi2_input: endpoint@1 { reg = <1>; - remote-endpoint = <&csidphy_out>; + remote-endpoint = <&dphy2_out>; data-lanes = <1 2>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10.dtsi index 6c47a166f131..8e3869357595 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10.dtsi @@ -53,41 +53,119 @@ status = "okay"; }; -&csi_dphy { +&csi2_dphy_hw { status = "okay"; +}; +&csi2_dphy0 { + status = "disabled"; + /* + * dphy0 only used for full mode, + * full mode and split mode are mutually exclusive + */ ports { #address-cells = <1>; #size-cells = <0>; + port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; - mipi_in_ucam0: endpoint@1 { + dphy0_in: endpoint@1 { reg = <1>; - remote-endpoint = <&ov5695_out>; - data-lanes = <1 2>; - }; - mipi_in_ucam1: endpoint@2 { - reg = <2>; remote-endpoint = <&gc8034_out>; data-lanes = <1 2 3 4>; }; }; + port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; - csidphy_out: endpoint@0 { - reg = <0>; + dphy0_out: endpoint@1 { + reg = <1>; remote-endpoint = <&isp0_in>; }; }; }; }; +&csi2_dphy1 { + status = "okay"; + + /* + * dphy1 only used for split mode, + * can be used concurrently with dphy2 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&csi2_dphy2 { + status = "okay"; + + /* + * dphy2 only used for split mode, + * can be used concurrently with dphy1 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy2_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc5025_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy2_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_csi2_input>; + }; + }; + }; +}; + /* * mipi_dphy0 needs to be enabled * when dsi0 is enabled @@ -165,6 +243,7 @@ status = "okay"; pinctrl-0 = <&i2c2m1_xfer>; + /* split mode: lane0/1 */ ov5695: ov5695@36 { status = "okay"; compatible = "ovti,ov5695"; @@ -183,12 +262,38 @@ rockchip,camera-module-lens-name = "CHT842-MD"; port { ov5695_out: endpoint { - remote-endpoint = <&mipi_in_ucam0>; + remote-endpoint = <&dphy1_in>; data-lanes = <1 2>; }; }; }; + /* split mode: lane:2/3 */ + gc5025: gc5025@37 { + status = "okay"; + compatible = "galaxycore,gc5025"; + reg = <0x37>; + clocks = <&pmucru CLK_WIFI>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&refclk_pins>; + reset-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + power-domains = <&power RK3568_PD_VI>; + /*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/ + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + gc5025_out: endpoint { + remote-endpoint = <&dphy2_in>; + data-lanes = <1 2>; + }; + }; + }; + + /* full mode: lane0-3 */ gc8034: gc8034@37 { compatible = "galaxycore,gc8034"; status = "okay"; @@ -206,12 +311,11 @@ rockchip,camera-module-lens-name = "CK8401"; port { gc8034_out: endpoint { - remote-endpoint = <&mipi_in_ucam1>; + remote-endpoint = <&dphy0_in>; data-lanes = <1 2 3 4>; }; }; }; - }; &i2c4 { @@ -269,6 +373,39 @@ power-supply = <&vcc3v3_lcd0_n>; }; +&mipi_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&dphy2_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + &mipi_dphy0 { status = "okay"; }; @@ -347,6 +484,17 @@ }; }; +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in: endpoint { + remote-endpoint = <&mipi_csi2_output>; + data-lanes = <1 2>; + }; + }; +}; + &rkcif_mmu { status = "okay"; }; @@ -368,7 +516,7 @@ isp0_in: endpoint@0 { reg = <0>; - remote-endpoint = <&csidphy_out>; + remote-endpoint = <&dphy1_out>; }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10.dtsi index d5bb04a3ecb6..d0b40d84b6ef 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10.dtsi @@ -48,7 +48,7 @@ status = "okay"; }; -&csi_dphy { +&csi2_dphy0 { status = "okay"; ports { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts b/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts index c0680184cf94..e1515ddc540f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts @@ -280,7 +280,7 @@ cpu-supply = <&vdd_cpu>; }; -&csi_dphy { +&csi2_dphy0 { status = "okay"; ports { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w6.dts b/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w6.dts index feb31ee80250..5e8f7013ad75 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w6.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w6.dts @@ -194,7 +194,7 @@ cpu-supply = <&vdd_cpu>; }; -&csi_dphy { +&csi2_dphy0 { status = "okay"; ports { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-k108.dts b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-k108.dts index 7b2d5fcfbcab..83bca1679180 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-k108.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-k108.dts @@ -240,7 +240,11 @@ cpu-supply = <&vdd_cpu>; }; -&csi_dphy { +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { status = "okay"; ports { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-rkg11.dts b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-rkg11.dts index 9f3bc55edc5d..01e7f2f559b7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-rkg11.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-rkg11.dts @@ -221,7 +221,11 @@ cpu-supply = <&vdd_cpu>; }; -&csi_dphy { +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { status = "okay"; ports { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet.dts b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet.dts index 2191d74ac9bb..7661ed1d8b50 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet.dts @@ -217,7 +217,11 @@ cpu-supply = <&vdd_cpu>; }; -&csi_dphy { +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { status = "okay"; ports { diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dtsi index 67917c881651..b03c788f2861 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dtsi @@ -107,7 +107,11 @@ status = "okay"; }; -&csi_dphy { +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { status = "okay"; ports { diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb5-ddr4-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb5-ddr4-v10.dtsi index a3f8e90901f2..0bc2685abc42 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb5-ddr4-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb5-ddr4-v10.dtsi @@ -98,7 +98,7 @@ status = "okay"; }; -&csi_dphy { +&csi2_dphy0 { status = "okay"; ports { diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10.dtsi index 1994efeda9d9..0e1e30d789f8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10.dtsi @@ -253,7 +253,7 @@ /delete-node/ mxc6655xa@15; }; -&csi_dphy { +&csi2_dphy0 { status = "okay"; ports { diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 88923d43ea99..82e7b36539f9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -23,6 +23,9 @@ #size-cells = <2>; aliases { + csi2dphy0 = &csi2_dphy0; + csi2dphy1 = &csi2_dphy1; + csi2dphy2 = &csi2_dphy2; dsi0 = &dsi0; dsi1 = &dsi1; ethernet0 = &gmac0; @@ -3048,8 +3051,8 @@ status = "disabled"; }; - csi_dphy: csi-dphy@fe870000 { - compatible = "rockchip,rk3568-csi-dphy"; + csi2_dphy_hw: csi2-dphy-hw@fe870000 { + compatible = "rockchip,rk3568-csi2-dphy-hw"; reg = <0x0 0xfe870000 0x0 0x1000>; clocks = <&cru PCLK_MIPICSIPHY>; clock-names = "pclk"; @@ -3057,12 +3060,32 @@ status = "disabled"; }; - csi_dphy1: csi-dphy@fe870000 { - compatible = "rockchip,rk3568-csi-dphy"; - reg = <0x0 0xfe870000 0x0 0x1000>; - clocks = <&cru PCLK_MIPICSIPHY>; - clock-names = "pclk"; - rockchip,grf = <&grf>; + /* + * csi2_dphy0: used for csi2 dphy full mode, + is mutually exclusive with + csi2_dphy1 and csi2_dphy2 + * csi2_dphy1: used for csi2 dphy split mode, + physical lanes use lane0 and lane1, + can be used with csi2_dphy2 parallel + * csi2_dphy2: used for csi2 dphy split mode, + physical lanes use lane2 and lane3, + can be used with csi2_dphy1 parallel + */ + csi2_dphy0: csi2-dphy0 { + compatible = "rockchip,rk3568-csi2-dphy"; + rockchip,hw = <&csi2_dphy_hw>; + status = "disabled"; + }; + + csi2_dphy1: csi2-dphy1 { + compatible = "rockchip,rk3568-csi2-dphy"; + rockchip,hw = <&csi2_dphy_hw>; + status = "disabled"; + }; + + csi2_dphy2: csi2-dphy2 { + compatible = "rockchip,rk3568-csi2-dphy"; + rockchip,hw = <&csi2_dphy_hw>; status = "disabled"; };