From 2703184e9de2eb545138ddb6cac5c31b27fe1df3 Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Mon, 11 Jul 2022 12:13:20 +0800 Subject: [PATCH] drm/rockchp: dw-dp: set a suitable hsync limit value In actual test, the min hsync value is 9, So it just need filter the display mode whose hsync value is less than 9. Signed-off-by: Zhang Yubing Change-Id: I06bc52c1f8b45894ee9813c8d014e6a9e3f48df6 --- drivers/gpu/drm/rockchip/dw-dp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-dp.c b/drivers/gpu/drm/rockchip/dw-dp.c index 5ffe1bedb632..98eacca211fe 100644 --- a/drivers/gpu/drm/rockchip/dw-dp.c +++ b/drivers/gpu/drm/rockchip/dw-dp.c @@ -2023,6 +2023,9 @@ static int dw_dp_bridge_mode_valid(struct drm_bridge *bridge, if (dp->split_mode) drm_mode_convert_to_origin_mode(&m); + if (m.hsync_end - m.hsync_start <= 8) + return MODE_HSYNC_NARROW; + if (info->color_formats & DRM_COLOR_FORMAT_YCRCB420 && link->vsc_sdp_extension_for_colorimetry_supported && (drm_mode_is_420_only(info, &m) || drm_mode_is_420_also(info, &m))) @@ -2038,9 +2041,6 @@ static int dw_dp_bridge_mode_valid(struct drm_bridge *bridge, drm_mode_is_420_only(info, &m)) return MODE_NO_420; - if (m.hsync_end - m.hsync_start < 32) - return MODE_HSYNC_NARROW; - if (!dw_dp_bandwidth_ok(dp, &m, min_bpp, link->lanes, link->rate)) return MODE_CLOCK_HIGH;