From 275c8705e576de90245e23a3f8cf45c872d4e724 Mon Sep 17 00:00:00 2001 From: Nagireddy Annem Date: Tue, 15 Nov 2022 09:35:26 +0530 Subject: [PATCH] ANDROID: irqchip/irq-gic-v3: Add vendor hook for gic suspend This change adds vendor hook for gic suspend syscore ops callback. And it is invoked during deepsleep and hibernation to store gic register snapshot. Bug: 279879797 Change-Id: I4e3729afa4daf18d73e00ee9601b6da72a578b4a Signed-off-by: Nagireddy Annem Signed-off-by: Shreyas K K --- drivers/android/vendor_hooks.c | 1 + drivers/irqchip/irq-gic-v3.c | 32 ++++++++++++++++++++---------- include/linux/irqchip/arm-gic-v3.h | 4 ++++ include/trace/hooks/gic_v3.h | 4 ++++ 4 files changed, 31 insertions(+), 10 deletions(-) diff --git a/drivers/android/vendor_hooks.c b/drivers/android/vendor_hooks.c index c597baaebc5c..8d209492daf0 100644 --- a/drivers/android/vendor_hooks.c +++ b/drivers/android/vendor_hooks.c @@ -227,6 +227,7 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_panic_unhandled); EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_arm64_serror_panic); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_disable_thermal_cooling_stats); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_gic_resume); +EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_gic_v3_suspend); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_audio_usb_offload_connect); EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_audio_usb_offload_disconnect); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_kswapd_per_node); diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index f351c15110a7..a1413e6d65bc 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -211,10 +211,11 @@ static void gic_do_wait_for_rwp(void __iomem *base, u32 bit) } /* Wait for completion of a distributor change */ -static void gic_dist_wait_for_rwp(void) +void gic_v3_dist_wait_for_rwp(void) { gic_do_wait_for_rwp(gic_data.dist_base, GICD_CTLR_RWP); } +EXPORT_SYMBOL_GPL(gic_v3_dist_wait_for_rwp); /* Wait for completion of a redistributor change */ static void gic_redist_wait_for_rwp(void) @@ -361,7 +362,7 @@ static void gic_mask_irq(struct irq_data *d) if (gic_irq_in_rdist(d)) gic_redist_wait_for_rwp(); else - gic_dist_wait_for_rwp(); + gic_v3_dist_wait_for_rwp(); } static void gic_eoimode1_mask_irq(struct irq_data *d) @@ -817,7 +818,7 @@ static bool gic_has_group0(void) return val != 0; } -static void __init gic_dist_init(void) +void gic_v3_dist_init(void) { unsigned int i; u64 affinity; @@ -826,7 +827,7 @@ static void __init gic_dist_init(void) /* Disable the distributor */ writel_relaxed(0, base + GICD_CTLR); - gic_dist_wait_for_rwp(); + gic_v3_dist_wait_for_rwp(); /* * Configure SPIs as non-secure Group-1. This will only matter @@ -863,7 +864,7 @@ static void __init gic_dist_init(void) /* Enable distributor with ARE, Group1, and wait for it to drain */ writel_relaxed(val, base + GICD_CTLR); - gic_dist_wait_for_rwp(); + gic_v3_dist_wait_for_rwp(); /* * Set all global interrupts to the boot CPU only. ARE must be @@ -880,6 +881,7 @@ static void __init gic_dist_init(void) gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8); } } +EXPORT_SYMBOL_GPL(gic_v3_dist_init); static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) { @@ -1175,7 +1177,7 @@ static int gic_dist_supports_lpis(void) !gicv3_nolpi); } -static void gic_cpu_init(void) +void gic_v3_cpu_init(void) { void __iomem *rbase; int i; @@ -1202,6 +1204,7 @@ static void gic_cpu_init(void) /* initialise system registers */ gic_cpu_sys_reg_init(); } +EXPORT_SYMBOL_GPL(gic_v3_cpu_init); #ifdef CONFIG_SMP @@ -1210,7 +1213,7 @@ static void gic_cpu_init(void) static int gic_starting_cpu(unsigned int cpu) { - gic_cpu_init(); + gic_v3_cpu_init(); if (gic_dist_supports_lpis()) its_cpu_init(); @@ -1401,8 +1404,15 @@ static void gic_resume(void) trace_android_vh_gic_resume(&gic_data); } +static int gic_v3_suspend(void) +{ + trace_android_vh_gic_v3_suspend(&gic_data); + return 0; +} + static struct syscore_ops gic_syscore_ops = { - .resume = gic_resume, + .resume = gic_v3_resume, + .suspend = gic_v3_suspend, }; static void gic_syscore_init(void) @@ -1412,6 +1422,8 @@ static void gic_syscore_init(void) #else static inline void gic_syscore_init(void) { } +void gic_v3_resume(void) { } +static int gic_v3_suspend(void) { return 0; } #endif @@ -1899,8 +1911,8 @@ static int __init gic_init_bases(void __iomem *dist_base, gic_update_rdist_properties(); - gic_dist_init(); - gic_cpu_init(); + gic_v3_dist_init(); + gic_v3_cpu_init(); gic_smp_init(); gic_cpu_pm_init(); gic_syscore_init(); diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index d2e617bffb3a..ae2701122af8 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -669,6 +669,10 @@ static inline bool gic_enable_sre(void) return !!(val & ICC_SRE_EL1_SRE); } +void gic_v3_dist_init(void); +void gic_v3_cpu_init(void); +void gic_v3_dist_wait_for_rwp(void); +void gic_v3_resume(void); #endif diff --git a/include/trace/hooks/gic_v3.h b/include/trace/hooks/gic_v3.h index 0f81993df161..8bafe0abe608 100644 --- a/include/trace/hooks/gic_v3.h +++ b/include/trace/hooks/gic_v3.h @@ -14,6 +14,7 @@ */ struct irq_data; struct cpumask; +struct gic_chip_data_v3; DECLARE_HOOK(android_vh_gic_v3_affinity_init, TP_PROTO(int irq, u32 offset, u64 *affinity), TP_ARGS(irq, offset, affinity)); @@ -23,6 +24,9 @@ DECLARE_RESTRICTED_HOOK(android_rvh_gic_v3_set_affinity, void __iomem *rbase, u64 redist_stride), TP_ARGS(d, mask_val, affinity, force, base, rbase, redist_stride), 1); +DECLARE_HOOK(android_vh_gic_v3_suspend, + TP_PROTO(struct gic_chip_data_v3 *gd), + TP_ARGS(gd)); #endif /* _TRACE_HOOK_GIC_V3_H */ /* This part must be outside protection */