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rk3026: add clock_data support
This commit is contained in:
chenxing
2869
arch/arm/mach-rk3026/clock_data.c
Executable file
2869
arch/arm/mach-rk3026/clock_data.c
Executable file
File diff suppressed because it is too large
Load Diff
561
arch/arm/mach-rk3026/include/mach/cru.h
Executable file
561
arch/arm/mach-rk3026/include/mach/cru.h
Executable file
@@ -0,0 +1,561 @@
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#ifndef __MACH_CRU_H
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#define __MACH_CRU_H
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enum rk_plls_id {
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APLL_ID = 0,
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DPLL_ID,
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CPLL_ID,
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GPLL_ID,
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END_PLL_ID,
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};
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/*****cru reg offset*****/
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#define CRU_MODE_CON 0x40
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#define CRU_CLKSEL_CON 0x44
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#define CRU_CLKGATE_CON 0xd0
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#define CRU_GLB_SRST_FST 0x100
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#define CRU_GLB_SRST_SND 0x104
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#define CRU_SOFTRST_CON 0x110
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#define PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
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#define CRU_CLKSELS_CON_CNT (35)
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#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + ((i) * 4))
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#define CRU_CLKGATES_CON_CNT (10)
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#define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4))
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#define CRU_SOFTRSTS_CON_CNT (9)
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#define CRU_SOFTRSTS_CON(i) (CRU_SOFTRST_CON + ((i) * 4))
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#define CRU_MISC_CON (0x134)
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#define CRU_GLB_CNT_TH (0x140)
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/*PLL_CON 0,1,2*/
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#define PLL_PWR_ON (0)
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#define PLL_PWR_DN (1)
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#define PLL_BYPASS (1 << 15)
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#define PLL_NO_BYPASS (0 << 15)
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//con0
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#define PLL_BYPASS_SHIFT (15)
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#define PLL_POSTDIV1_MASK (0x7)
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#define PLL_POSTDIV1_SHIFT (12)
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#define PLL_FBDIV_MASK (0xfff)
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#define PLL_FBDIV_SHIFT (0)
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//con1
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#define PLL_RSTMODE_SHIFT (15)
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#define PLL_RST_SHIFT (14)
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#define PLL_PWR_DN_SHIFT (13)
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#define PLL_DSMPD_SHIFT (12)
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#define PLL_LOCK_SHIFT (10)
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#define PLL_POSTDIV2_MASK (0x7)
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#define PLL_POSTDIV2_SHIFT (6)
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#define PLL_REFDIV_MASK (0x3f)
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#define PLL_REFDIV_SHIFT (0)
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//con2
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#define PLL_FOUT4PHASE_PWR_DN_SHIFT (27)
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#define PLL_FOUTVCO_PWR_DN_SHIFT (26)
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#define PLL_FOUTPOSTDIV_PWR_DN_SHIFT (25)
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#define PLL_DAC_PWR_DN_SHIFT (24)
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#define PLL_FRAC_MASK (0xffffff)
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#define PLL_FRAC_SHIFT (0)
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/********************************************************************/
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#define CRU_GET_REG_BIT_VAL(reg, bits_shift) (((reg) >> (bits_shift)) & (0x1))
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#define CRU_GET_REG_BITS_VAL(reg, bits_shift, msk) (((reg) >> (bits_shift)) & (msk))
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#define CRU_SET_BIT(val, bits_shift) (((val) & (0x1)) << (bits_shift))
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#define CRU_SET_BITS(val, bits_shift, msk) (((val) & (msk)) << (bits_shift))
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#define CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16))
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#define CRU_W_MSK_SETBITS(val, bits_shift, msk) (CRU_W_MSK(bits_shift, msk) \
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| CRU_SET_BITS(val, bits_shift, msk))
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#define CRU_W_MSK_SETBIT(val, bits_shift) (CRU_W_MSK(bits_shift, 0x1) \
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| CRU_SET_BIT(val, bits_shift))
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#define PLL_SET_REFDIV(val) CRU_W_MSK_SETBITS(val, PLL_REFDIV_SHIFT, PLL_REFDIV_MASK)
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#define PLL_SET_FBDIV(val) CRU_W_MSK_SETBITS(val, PLL_FBDIV_SHIFT, PLL_FBDIV_MASK)
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#define PLL_SET_POSTDIV1(val) CRU_W_MSK_SETBITS(val, PLL_POSTDIV1_SHIFT, PLL_POSTDIV1_MASK)
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#define PLL_SET_POSTDIV2(val) CRU_W_MSK_SETBITS(val, PLL_POSTDIV2_SHIFT, PLL_POSTDIV2_MASK)
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#define PLL_SET_FRAC(val) CRU_SET_BITS(val, PLL_FRAC_SHIFT, PLL_FRAC_MASK)
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#define PLL_GET_REFDIV(reg) CRU_GET_REG_BITS_VAL(reg, PLL_REFDIV_SHIFT, PLL_REFDIV_MASK)
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#define PLL_GET_FBDIV(reg) CRU_GET_REG_BITS_VAL(reg, PLL_FBDIV_SHIFT, PLL_FBDIV_MASK)
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#define PLL_GET_POSTDIV1(reg) CRU_GET_REG_BITS_VAL(reg, PLL_POSTDIV1_SHIFT, PLL_POSTDIV1_MASK)
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#define PLL_GET_POSTDIV2(reg) CRU_GET_REG_BITS_VAL(reg, PLL_POSTDIV2_SHIFT, PLL_POSTDIV2_MASK)
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#define PLL_GET_FRAC(reg) CRU_GET_REG_BITS_VAL(reg, PLL_FRAC_SHIFT, PLL_FRAC_MASK)
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//#define APLL_SET_BYPASS(val) CRU_SET_BIT(val, PLL_BYPASS_SHIFT)
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#define PLL_SET_DSMPD(val) CRU_W_MSK_SETBIT(val, PLL_DSMPD_SHIFT)
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#define PLL_GET_DSMPD(reg) CRU_GET_REG_BIT_VAL(reg, PLL_DSMPD_SHIFT)
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/*******************MODE BITS***************************/
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#define PLL_MODE_MSK(id) (0x1 << ((id) * 4))
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#define PLL_MODE_SHIFT(id) ((id) * 4)
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#define PLL_MODE_SLOW(id) (CRU_W_MSK_SETBIT(0x0, PLL_MODE_SHIFT(id)))
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#define PLL_MODE_NORM(id) (CRU_W_MSK_SETBIT(0x1, PLL_MODE_SHIFT(id)))
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/*******************CLKSEL0 BITS***************************/
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#define CLK_SET_DIV_CON_SUB1(val, bits_shift, msk) CRU_W_MSK_SETBITS((val - 1), bits_shift, msk)
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#define CPU_CLK_PLL_SEL_SHIFT (13)
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#define CORE_CLK_PLL_SEL_SHIFT (7)
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#define SEL_APLL (0)
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#define SEL_GPLL (1)
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#define CPU_SEL_PLL(plls) CRU_W_MSK_SETBIT(plls, CPU_CLK_PLL_SEL_SHIFT)
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#define CORE_SEL_PLL(plls) CRU_W_MSK_SETBIT(plls, CORE_CLK_PLL_SEL_SHIFT)
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#define ACLK_CPU_DIV_MASK (0x1f)
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#define ACLK_CPU_DIV_SHIFT (8)
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#define A9_CORE_DIV_MASK (0x1f)
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#define A9_CORE_DIV_SHIFT (0)
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#define RATIO_11 (1)
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#define RATIO_21 (2)
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#define RATIO_41 (4)
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#define RATIO_81 (8)
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#define ACLK_CPU_DIV(val) CLK_SET_DIV_CON_SUB1(val, ACLK_CPU_DIV_SHIFT, ACLK_CPU_DIV_MASK)
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#define CLK_CORE_DIV(val) CLK_SET_DIV_CON_SUB1(val, A9_CORE_DIV_SHIFT, A9_CORE_DIV_MASK)
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/*******************CLKSEL1 BITS***************************/
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#define PCLK_CPU_DIV_MASK (0x7)
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#define PCLK_CPU_DIV_SHIFT (12)
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#define HCLK_CPU_DIV_MASK (0x3)
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#define HCLK_CPU_DIV_SHIFT (8)
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#define ACLK_CORE_DIV_MASK (0x7)
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#define ACLK_CORE_DIV_SHIFT (4)
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#define CORE_PERIPH_DIV_MASK (0xf)
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#define CORE_PERIPH_DIV_SHIFT (0)
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#define PCLK_CPU_DIV(val) CLK_SET_DIV_CON_SUB1(val, PCLK_CPU_DIV_SHIFT, PCLK_CPU_DIV_MASK)
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#define HCLK_CPU_DIV(val) CLK_SET_DIV_CON_SUB1(val, HCLK_CPU_DIV_SHIFT, HCLK_CPU_DIV_MASK)
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#define ACLK_CORE_DIV(val) CLK_SET_DIV_CON_SUB1(val, ACLK_CORE_DIV_SHIFT, ACLK_CORE_DIV_MASK)
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#define CLK_CORE_PERI_DIV(val) CLK_SET_DIV_CON_SUB1(val, CORE_PERIPH_DIV_SHIFT, CORE_PERIPH_DIV_MASK)
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/*******************clksel10***************************/
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#define PERI_PLL_SEL_SHIFT 15
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#define PERI_PCLK_DIV_MASK (0x3)
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#define PERI_PCLK_DIV_SHIFT (12)
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#define PERI_HCLK_DIV_MASK (0x3)
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#define PERI_HCLK_DIV_SHIFT (8)
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#define PERI_ACLK_DIV_MASK (0x1f)
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#define PERI_ACLK_DIV_SHIFT (0)
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#define SEL_2PLL_GPLL (0)
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#define SEL_2PLL_CPLL (1)
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#define PERI_CLK_SEL_PLL(plls) CRU_W_MSK_SETBIT(plls, PERI_PLL_SEL_SHIFT)
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#define PERI_SET_ACLK_DIV(val) CLK_SET_DIV_CON_SUB1(val, PERI_ACLK_DIV_SHIFT, PERI_ACLK_DIV_MASK)
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/*******************gate BITS***************************/
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#define CLK_GATE_CLKID_CONS(i) CRU_CLKGATES_CON((i) / 16)
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#define CLK_GATE(i) (1 << ((i)%16))
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#define CLK_UN_GATE(i) (0)
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#define CLK_GATE_W_MSK(i) (1 << (((i) % 16) + 16))
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#define CLK_GATE_CLKID(i) (16 * (i))
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enum cru_clk_gate {
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/* SCU CLK GATE 0 CON */
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CLK_GATE_CORE_PERIPH = CLK_GATE_CLKID(0),
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CLK_GATE_CPU_GPLL,
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CLK_GATE_DDRPHY_SRC,
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CLK_GATE_ACLK_CPU,
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CLK_GATE_HCLK_CPU,
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CLK_GATE_PCLK_CPU,
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CLK_GATE_CORE_GPLL,
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CLK_GATE_ACLK_CORE,
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CLK_GATE_DDRPHY_GPLL_SRC,
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CLK_GATE_I2S_SRC,
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CLK_GATE_I2S_FRAC_SRC,
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CLK_GATE_HCLK_DISP,
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CLK_GATE_CRYPTO,
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CLK_GATE_0RES13,
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CLK_GATE_0RES14,
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CLK_GATE_TESTCLK,
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CLK_GATE_TIMER0 = CLK_GATE_CLKID(1),
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CLK_GATE_TIMER1,
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CLK_GATE_1RES2,
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CLK_GATE_JTAG,
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CLK_GATE_ACLK_LCDC1_SRC,
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CLK_GATE_OTGPHY0,
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CLK_GATE_OTGPHY1,
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CLK_GATE_DLL_DDR,
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CLK_GATE_UART0_SRC,
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CLK_GATE_UART0_FRAC_SRC,
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CLK_GATE_UART1_SRC,
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CLK_GATE_UART1_FRAC_SRC,
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CLK_GATE_UART2_SRC,
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CLK_GATE_UART2_FRAC_SRC,
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CLK_GATE_DLL_GPU,
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CLK_GATE_DLL_CORE,
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CLK_GATE_PERIPH_SRC = CLK_GATE_CLKID(2),
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CLK_GATE_ACLK_PERIPH,
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CLK_GATE_HCLK_PERIPH,
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CLK_GATE_PCLK_PERIPH,
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CLK_GATE_2RES4,
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CLK_GATE_2RES5,
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CLK_GATE_2RES6,
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CLK_GATE_2RES7,
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CLK_GATE_SARADC_SRC,
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CLK_GATE_SPI0_SRC,
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CLK_GATE_2RES10,
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CLK_GATE_MMC0_SRC,
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CLK_GATE_2RES12,
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CLK_GATE_SDIO_SRC,
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CLK_GATE_EMMC_SRC,
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CLK_GATE_2RES15,
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CLK_GATE_ACLK_LCDC0_SRC = CLK_GATE_CLKID(3),
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CLK_GATE_DCLK_LCDC0_SRC,
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CLK_GATE_DCLK_LCDC1_SRC,
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CLK_GATE_PCLKIN_CIF,
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CLK_GATE_DCLK_EBC_SRC,
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CLK_GATE_HCLK_CRYPTO,
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CLK_GATE_HCLK_EMEM_PERI,
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CLK_GATE_CIF_OUT_SRC,
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CLK_GATE_PCLK_HDMI,
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CLK_GATE_ACLK_VEPU_SRC,
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CLK_GATE_3RES10,
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CLK_GATE_ACLK_VDPU_SRC,
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CLK_GATE_HCLK_VDPU,
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CLK_GATE_GPU_PRE,
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CLK_GATE_ACLK_GPS,
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CLK_GATE_3RES15,
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CLK_GATE_HCLK_PERI_AXI_MATRIX = CLK_GATE_CLKID(4),
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CLK_GATE_PCLK_PERI_AXI_MATRIX,
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CLK_GATE_ACLK_CPU_PERI,
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CLK_GATE_ACLK_PERI_AXI_MATRIX,
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CLK_GATE_4RES4,
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CLK_GATE_4RES5,
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CLK_GATE_4RES6,
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CLK_GATE_4RES7,
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CLK_GATE_4RES8,
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CLK_GATE_4RES9,
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CLK_GATE_ACLK_STRC_SYS,
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CLK_GATE_4RES11,
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CLK_GATE_ACLK_INTMEM,
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CLK_GATE_4RES13,
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CLK_GATE_4RES14,
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CLK_GATE_4RES15,
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CLK_GATE_5RES0 = CLK_GATE_CLKID(5),
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CLK_GATE_ACLK_DMAC2,
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CLK_GATE_PCLK_EFUSE,
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CLK_GATE_5RES3,
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CLK_GATE_PCLK_GRF,
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CLK_GATE_5RES5,
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CLK_GATE_HCLK_ROM,
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CLK_GATE_PCLK_DDRUPCTL,
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CLK_GATE_5RES8,
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CLK_GATE_HCLK_NANDC,
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CLK_GATE_HCLK_SDMMC0,
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CLK_GATE_HCLK_SDIO,
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CLK_GATE_5RES12,
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CLK_GATE_HCLK_OTG0,
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CLK_GATE_PCLK_ACODEC,
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CLK_GATE_5RES15,
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CLK_GATE_ACLK_LCDC0 = CLK_GATE_CLKID(6),
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CLK_GATE_HCLK_LCDC0,
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CLK_GATE_6RES2,
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CLK_GATE_6RES3,
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CLK_GATE_HCLK_CIF,
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CLK_GATE_ACLK_CIF,
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CLK_GATE_6RES6,
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CLK_GATE_6RES7,
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CLK_GATE_6RES8,
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CLK_GATE_6RES9,
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CLK_GATE_HCLK_RGA,
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CLK_GATE_ACLK_RGA,
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CLK_GATE_HCLK_VIO_BUS,
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CLK_GATE_ACLK_VIO0,
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CLK_GATE_6RES14,
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CLK_GATE_6RES15,
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CLK_GATE_HCLK_EMMC = CLK_GATE_CLKID(7),
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CLK_GATE_7RES1,
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CLK_GATE_HCLK_I2S,
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CLK_GATE_HCLK_OTG1,
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CLK_GATE_7RES4,
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CLK_GATE_7RES5,
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CLK_GATE_7RES6,
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CLK_GATE_PCLK_TIMER0,
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CLK_GATE_PCLK_TIMER1,
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CLK_GATE_7RES9,
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CLK_GATE_PCLK_PWM01,
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CLK_GATE_7RES11,
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CLK_GATE_PCLK_SPI0,
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CLK_GATE_7RES13,
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CLK_GATE_PCLK_SARADC,
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CLK_GATE_PCLK_WDT,
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CLK_GATE_PCLK_UART0 = CLK_GATE_CLKID(8),
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CLK_GATE_PCLK_UART1,
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CLK_GATE_PCLK_UART2,
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CLK_GATE_8RES3,
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CLK_GATE_PCLK_I2C0,
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CLK_GATE_PCLK_I2C1,
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CLK_GATE_PCLK_I2C2,
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CLK_GATE_PCLK_I2C3,
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CLK_GATE_8RES8,
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CLK_GATE_PCLK_GPIO0,
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CLK_GATE_PCLK_GPIO1,
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CLK_GATE_PCLK_GPIO2,
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CLK_GATE_PCLK_GPIO3,
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CLK_GATE_8RES13,
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CLK_GATE_8RES14,
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CLK_GATE_8RES15,
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CLK_GATE_CLK_CORE_DBG = CLK_GATE_CLKID(9),
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CLK_GATE_PCLK_DBG,
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CLK_GATE_9RES2,
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CLK_GATE_9RES3,
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CLK_GATE_CLK_L2C,
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CLK_GATE_HCLK_LCDC1,
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CLK_GATE_ACLK_LCDC1,
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CLK_GATE_HCLK_IEP,
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CLK_GATE_ACLK_IEP,
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CLK_GATE_HCLK_EBC,
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CLK_GATE_ACLK_VIO1,
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CLK_GATE_9RES11,
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CLK_GATE_9RES12,
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CLK_GATE_HCLK_USB_PERI,
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CLK_GATE_HCLK_PERI_ARBI,
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CLK_GATE_ACLK_PERI_NIU,
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CLK_GATE_MAX,
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};
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#define SOFT_RST_ID(i) (16 * (i))
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enum cru_soft_reset {
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SOFT_RST_CORE_SRST_WDT_SEL = SOFT_RST_ID(0),
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SOFT_RST_0RES1,
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SOFT_RST_MCORE,
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SOFT_RST_CORE0,
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SOFT_RST_CORE1,
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SOFT_RST_0RES5,
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SOFT_RST_0RES6,
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SOFT_RST_MCORE_DBG,
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SOFT_RST_CORE0_DBG,
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SOFT_RST_CORE1_DBG,
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SOFT_RST_CORE0_WDT,
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SOFT_RST_CORE1_WDT,
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SOFT_RST_0RES12,
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SOFT_RST_ACLK_CORE,
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SOFT_RST_STRC_SYS_AXI,
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SOFT_RST_L2C,
|
||||
|
||||
SOFT_RST_1RES0 = SOFT_RST_ID(1),
|
||||
SOFT_RST_CPUSYS_AHB,
|
||||
SOFT_RST_L2MEM_CON_AXI,
|
||||
SOFT_RST_AHB2APB,
|
||||
|
||||
SOFT_RST_1RES4,
|
||||
SOFT_RST_INTMEM,
|
||||
SOFT_RST_ROM,
|
||||
SOFT_RST_PERI_NIU,
|
||||
|
||||
SOFT_RST_I2S,
|
||||
SOFT_RST_DDR_DLL,
|
||||
SOFT_RST_GPU_DLL,
|
||||
SOFT_RST_TIMER0,
|
||||
|
||||
SOFT_RST_TIMER1,
|
||||
SOFT_RST_CORE_DLL,
|
||||
SOFT_RST_EFUSE_APB,
|
||||
SOFT_RST_ACODEC,
|
||||
|
||||
SOFT_RST_GPIO0 = SOFT_RST_ID(2),
|
||||
SOFT_RST_GPIO1,
|
||||
SOFT_RST_GPIO2,
|
||||
SOFT_RST_GPIO3,
|
||||
|
||||
SOFT_RST_2RES4,
|
||||
SOFT_RST_2RES5,
|
||||
SOFT_RST_2RES6,
|
||||
SOFT_RST_UART0,
|
||||
|
||||
SOFT_RST_UART1,
|
||||
SOFT_RST_UART2,
|
||||
SOFT_RST_2RES10,
|
||||
SOFT_RST_I2C0,
|
||||
|
||||
SOFT_RST_I2C1,
|
||||
SOFT_RST_I2C2,
|
||||
SOFT_RST_I2C3,
|
||||
SOFT_RST_2RES15,
|
||||
|
||||
SOFT_RST_PWM0 = SOFT_RST_ID(3),
|
||||
SOFT_RST_PWM1,
|
||||
SOFT_RST_DAP_PO,
|
||||
SOFT_RST_DAP,
|
||||
|
||||
SOFT_RST_DAP_SYS,
|
||||
SOFT_RST_CRYPTO,
|
||||
SOFT_RST_3RES6,
|
||||
SOFT_RST_GRF,
|
||||
|
||||
SOFT_RST_3RES8,
|
||||
SOFT_RST_PERIPHSYS_AXI,
|
||||
SOFT_RST_PERIPHSYS_AHB,
|
||||
SOFT_RST_PERIPHSYS_APB,
|
||||
|
||||
SOFT_RST_PWM2,
|
||||
SOFT_RST_CPU_PERI,
|
||||
SOFT_RST_EMEM_PERI,
|
||||
SOFT_RST_USB_PERI,
|
||||
|
||||
SOFT_RST_DMA2 = SOFT_RST_ID(4),
|
||||
SOFT_RST_4RES1,
|
||||
SOFT_RST_4RES2,
|
||||
SOFT_RST_GPS,
|
||||
|
||||
SOFT_RST_NANDC,
|
||||
SOFT_RST_USBOTG0,
|
||||
SOFT_RST_4RES6,
|
||||
SOFT_RST_OTGC0,
|
||||
|
||||
SOFT_RST_USBOTG1,
|
||||
SOFT_RST_4RES9,
|
||||
SOFT_RST_OTGC1,
|
||||
SOFT_RST_4RES11,
|
||||
|
||||
SOFT_RST_4RES12,
|
||||
SOFT_RST_4RES13,
|
||||
SOFT_RST_4RES14,
|
||||
SOFT_RST_DDRMSCH,
|
||||
|
||||
SOFT_RST_5RES0 = SOFT_RST_ID(5),
|
||||
SOFT_RST_MMC0,
|
||||
SOFT_RST_SDIO,
|
||||
SOFT_RST_EMMC,
|
||||
|
||||
SOFT_RST_SPI0,
|
||||
SOFT_RST_5RES5,
|
||||
SOFT_RST_WDT,
|
||||
SOFT_RST_SARADC,
|
||||
|
||||
SOFT_RST_DDRPHY,
|
||||
SOFT_RST_DDRPHY_APB,
|
||||
SOFT_RST_DDRCTRL,
|
||||
SOFT_RST_DDRCTRL_APB,
|
||||
|
||||
SOFT_RST_5RES12,
|
||||
SOFT_RST_5RES13,
|
||||
SOFT_RST_5RES14,
|
||||
SOFT_RST_5RES15,
|
||||
|
||||
SOFT_RST_HDMI_PCLK = SOFT_RST_ID(6),
|
||||
SOFT_RST_VIO_ARBI_AHB,
|
||||
SOFT_RST_VIO0_AXI,
|
||||
SOFT_RST_VIO_BUS_AHB,
|
||||
|
||||
SOFT_RST_LCDC0_AXI,
|
||||
SOFT_RST_LCDC0_AHB,
|
||||
SOFT_RST_LCDC0_DCLK,
|
||||
SOFT_RST_UTMI0,
|
||||
|
||||
SOFT_RST_UTMI1,
|
||||
SOFT_RST_USBPOR,
|
||||
SOFT_RST_IEP_AXI,
|
||||
SOFT_RST_IEP_AHB,
|
||||
|
||||
SOFT_RST_RGA_AXI,
|
||||
SOFT_RST_RGA_AHB,
|
||||
SOFT_RST_CIF0,
|
||||
SOFT_RST_6RES15,
|
||||
|
||||
SOFT_RST_VCODEC_AXI = SOFT_RST_ID(7),
|
||||
SOFT_RST_VCODEC_AHB,
|
||||
SOFT_RST_VIO1_AXI,
|
||||
SOFT_RST_7RES3,
|
||||
|
||||
SOFT_RST_VCODEC_NIU_AXI,
|
||||
SOFT_RST_LCDC1_AXI,
|
||||
SOFT_RST_LCDC1_AHB,
|
||||
SOFT_RST_LCDC1_DCLK,
|
||||
|
||||
SOFT_RST_GPU,
|
||||
SOFT_RST_7RES9,
|
||||
SOFT_RST_GPU_NIU_AXI,
|
||||
SOFT_RST_EBC_AXI,
|
||||
|
||||
SOFT_RST_EBC_AHB,
|
||||
SOFT_RST_7RES13,
|
||||
SOFT_RST_7RES14,
|
||||
SOFT_RST_7RES15,
|
||||
|
||||
SOFT_RST_8RES0 = SOFT_RST_ID(8),
|
||||
SOFT_RST_8RES1,
|
||||
SOFT_RST_CORE_DBG,
|
||||
SOFT_RST_DBG_APB,
|
||||
|
||||
SOFT_RST_8RES4,
|
||||
SOFT_RST_8RES5,
|
||||
SOFT_RST_8RES6,
|
||||
SOFT_RST_8RES7,
|
||||
|
||||
SOFT_RST_8RES8,
|
||||
SOFT_RST_8RES9,
|
||||
SOFT_RST_8RES10,
|
||||
SOFT_RST_8RES11,
|
||||
|
||||
SOFT_RST_8RES12,
|
||||
SOFT_RST_8RES13,
|
||||
SOFT_RST_8RES14,
|
||||
SOFT_RST_8RES15,
|
||||
|
||||
SOFT_RST_MAX,
|
||||
};
|
||||
|
||||
/*****cru reg end*****/
|
||||
static inline void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
|
||||
{
|
||||
const void __iomem *reg = RK2928_CRU_BASE + CRU_SOFTRSTS_CON(idx >> 4);
|
||||
u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
|
||||
writel_relaxed(val, reg);
|
||||
dsb();
|
||||
}
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user