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tm2: make emmc run high speed [1/1]

Browse Source 
PD#SWPL-5658

Problem:
emmc run hs200 report cmd18 rx data crc

Solution:
emmc run high speed first

Verify:
passed on t962e2_ab319

Change-Id: Iaeef33e38f7c5130ebfd0e7c5886459b8138a803
Signed-off-by: ruixuan.li <ruixuan.li@amlogic.com>
This commit is contained in:
ruixuan.li
2019-04-01 14:12:07 +08:00
committed by Dongjin Kim
parent 84793b0b4b
commit 28597e230b
10 changed files with 45 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/amlogic/mesontm2.dtsi
View File

@@ -1148,7 +1148,7 @@
sd_emmc_c: emmc@ffe07000 {
status = "disabled";
compatible = "amlogic, meson-mmc-tl1";
compatible = "amlogic, meson-mmc-tm2";
reg = <0xffe07000 0x800>;
interrupts = <0 191 1>;
pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins";
@@ -1157,7 +1157,7 @@
clocks = <&clkc CLKID_SD_EMMC_C>,
<&clkc CLKID_SD_EMMC_C_P0_COMP>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_FCLK_DIV5>,
<&clkc CLKID_FCLK_DIV2P5>,
<&clkc CLKID_GP0_PLL>,
<&xtal>;
clock-names = "core","clkin0","clkin1","clkin2","clkin3","xtal";

2
arch/arm/boot/dts/amlogic/tm2_pxp.dts
View File

@@ -1003,7 +1003,7 @@
}; /* end of pinctrl_aobus */
&sd_emmc_b {
status = "disabled";
status = "okay";
sd {
caps = "MMC_CAP_4_BIT_DATA",
"MMC_CAP_MMC_HIGHSPEED",

4
arch/arm/boot/dts/amlogic/tm2_t962e2_ab311.dts
View File

@@ -1733,9 +1733,9 @@
"MMC_CAP_ERASE",
"MMC_CAP_CMD23",
"MMC_CAP_DRIVER_TYPE_D";
caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
//caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
f_min = <400000>;
f_max = <198000000>;
f_max = <50000000>;
};
};

6
arch/arm/boot/dts/amlogic/tm2_t962e2_ab319.dts
View File

@@ -1614,14 +1614,14 @@
"MMC_CAP_MMC_HIGHSPEED",
"MMC_CAP_SD_HIGHSPEED",
"MMC_CAP_NONREMOVABLE",
"MMC_CAP_1_8V_DDR",
/*"MMC_CAP_1_8V_DDR",*/
"MMC_CAP_HW_RESET",
"MMC_CAP_ERASE",
"MMC_CAP_CMD23";
caps2 = "MMC_CAP2_HS200";
//caps2 = "MMC_CAP2_HS200";
/* "MMC_CAP2_HS400";*/
f_min = <400000>;
f_max = <200000000>;
f_max = <50000000>;
};
};

4
arch/arm64/boot/dts/amlogic/mesontm2.dtsi
View File

@@ -1128,7 +1128,7 @@
sd_emmc_c: emmc@ffe07000 {
status = "disabled";
compatible = "amlogic, meson-mmc-tl1";
compatible = "amlogic, meson-mmc-tm2";
reg = <0x0 0xffe07000 0x0 0x800>;
interrupts = <0 191 1>;
pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins";
@@ -1137,7 +1137,7 @@
clocks = <&clkc CLKID_SD_EMMC_C>,
<&clkc CLKID_SD_EMMC_C_P0_COMP>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_FCLK_DIV5>,
<&clkc CLKID_FCLK_DIV2P5>,
<&clkc CLKID_GP0_PLL>,
<&xtal>;
clock-names = "core","clkin0","clkin1","clkin2","clkin3","xtal";

2
arch/arm64/boot/dts/amlogic/tm2_pxp.dts
View File

@@ -998,7 +998,7 @@
}; /* end of pinctrl_aobus */
&sd_emmc_b {
status = "disabled";
status = "okay";
sd {
caps = "MMC_CAP_4_BIT_DATA",
"MMC_CAP_MMC_HIGHSPEED",

4
arch/arm64/boot/dts/amlogic/tm2_t962e2_ab311.dts
View File

@@ -1692,9 +1692,9 @@
"MMC_CAP_ERASE",
"MMC_CAP_CMD23",
"MMC_CAP_DRIVER_TYPE_D";
caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
//caps2 = "MMC_CAP2_HS200"; /* "MMC_CAP2_HS400";*/
f_min = <400000>;
f_max = <198000000>;
f_max = <50000000>;
};
};

9
arch/arm64/boot/dts/amlogic/tm2_t962e2_ab319.dts
View File

@@ -1160,7 +1160,7 @@
sd_emmc_b: sd@ffe05000 {
status = "okay";
compatible = "amlogic, meson-mmc-tl1";
compatible = "amlogic, meson-mmc-tm2";
reg = <0x0 0xffe05000 0x0 0x800>;
interrupts = <0 190 1>;
@@ -1613,14 +1613,13 @@
"MMC_CAP_MMC_HIGHSPEED",
"MMC_CAP_SD_HIGHSPEED",
"MMC_CAP_NONREMOVABLE",
"MMC_CAP_1_8V_DDR",
/*"MMC_CAP_1_8V_DDR",*/
"MMC_CAP_HW_RESET",
"MMC_CAP_ERASE",
"MMC_CAP_CMD23";
caps2 = "MMC_CAP2_HS200";
/* "MMC_CAP2_HS400";*/
/*caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";*/
f_min = <400000>;
f_max = <200000000>;
f_max = <50000000>;
};
};

27
drivers/amlogic/mmc/aml_sd_emmc.c
View File

@@ -3668,6 +3668,29 @@ static struct meson_mmc_data mmc_data_sm1 = {
.sdmmc.sdr104.core_phase = 2,
.sdmmc.sdr104.tx_phase = 0,
};
static struct meson_mmc_data mmc_data_tm2 = {
.chip_type = MMC_CHIP_TM2,
.port_a_base = 0xffe03000,
.port_b_base = 0xffe05000,
.port_c_base = 0xffe07000,
.pinmux_base = 0xff634400,
.clksrc_base = 0xff63c000,
.ds_pin_poll = 0x3a,
.ds_pin_poll_en = 0x48,
.ds_pin_poll_bit = 13,
.sdmmc.init.core_phase = 3,
.sdmmc.init.tx_phase = 0,
.sdmmc.init.rx_phase = 0,
.sdmmc.hs.core_phase = 3,
.sdmmc.ddr.core_phase = 2,
.sdmmc.hs2.core_phase = 2,
.sdmmc.hs4.core_phase = 0,
.sdmmc.hs4.tx_delay = 16,
.sdmmc.sd_hs.core_phase = 2,
.sdmmc.sdr104.core_phase = 2,
};
static const struct of_device_id meson_mmc_of_match[] = {
{
.compatible = "amlogic, meson-mmc-gxbb",
@@ -3725,6 +3748,10 @@ static const struct of_device_id meson_mmc_of_match[] = {
.compatible = "amlogic, meson-mmc-sm1",
.data = &mmc_data_sm1,
},
{
.compatible = "amlogic, meson-mmc-tm2",
.data = &mmc_data_tm2,
},
{}
};

1
include/linux/amlogic/sd.h
View File

@@ -193,6 +193,7 @@ enum mmc_chip_e {
MMC_CHIP_TL1 = 0X2b,
MMC_CHIP_G12B = 0x29b,
MMC_CHIP_SM1 = 0X2C,
MMC_CHIP_TM2 = 0X2D,
};
struct mmc_phase {