From 288abb8b19f74fd2f200b5e65c401edbebbb41cb Mon Sep 17 00:00:00 2001 From: Sajid Dalvi Date: Tue, 20 Feb 2024 13:20:17 -0600 Subject: [PATCH] ANDROID: PCI: dwc: Wait for the link only if it has been started In dw_pcie_host_init() regardless of whether the link has been started or not, the code waits for the link to come up. Even in cases where start_link() is not defined the code ends up spinning in a loop for 1 second. Since in some systems dw_pcie_host_init() gets called during probe, this one second loop for each pcie interface instance ends up extending the boot time. Wait for the link up in only if the start_link() is defined. The patch submitted to the upstream kernel (see link below) was not accepted due to no upstream user. The change here is a simplified version of that patch, which will wait for a link only if start_link ops has been defined. Also, this patch was already applied before in https://r.android.com/2548250 but the functionality was lost after https://lore.kernel.org/all/20220624143428.8334-14-Sergey.Semin@baikalelectronics.ru/ was pulled in from the LTS merge. This patch restores the functionality (of removing the delay) which was lost during the LTS merge. Bug: 315052790 Link: https://lore.kernel.org/all/20240112093006.2832105-1-ajayagarwal@google.com/ Change-Id: I4e8d00f6195062728417e41ddd51072880676920 Signed-off-by: Sajid Dalvi --- drivers/pci/controller/dwc/pcie-designware-host.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index fe0fd88e95eb..f0967cbb48f2 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -411,8 +411,10 @@ int dw_pcie_host_init(struct pcie_port *pp) if (ret) goto err_free_msi; - /* Ignore errors, the link may come up later */ - dw_pcie_wait_for_link(pci); + if (pci->ops && pci->ops->start_link) { + /* Ignore errors, the link may come up later */ + dw_pcie_wait_for_link(pci); + } } bridge->sysdata = pp;