shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-09 12:17:12 +09:00
Code Issues Packages Projects Releases Wiki Activity

rk3066B: compatible with rk3188 plus pll config, fix compile error

Browse Source
This commit is contained in:
chenxing
2013-05-10 18:06:04 +08:00
parent dd25dbca60
commit 28905e328b
1 changed files with 7 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
arch/arm/mach-rk30/include/mach/cru-rk3066b.h
View File

@@ -71,19 +71,16 @@ enum rk_plls_id {
#define PLL_CLKF_SET(val) (PLL_CLKF(val) | CRU_W_MSK(PLL_NF_SHIFT, PLL_NF_MSK))
/*******************PLL CON2 BITS***************************/
#if 0
#define PLL_BWADJ_MSK (0xfff)
// "BWADJ" Just compatible with RK3188 plus
#define PLL_BWADJ_MSK (0xfff & 0x000)
#define PLL_BWADJ_SHIFT (0)
#define PLL_CLK_BWADJ_SET(val) ((val) | CRU_W_MSK(PLL_BWADJ_SHIFT, PLL_BWADJ_MSK))
#endif
/*******************PLL CON3 BITS***************************/
#if 0
#define PLL_REST_MSK (1 << 5)
#define PLL_REST_W_MSK (PLL_REST_MSK << 16)
#define PLL_REST (1 << 5)
#define PLL_REST_RESM (0 << 5)
#endif
// "RESET" Just compatible with RK3188 plus
#define PLL_RESET_MSK ((1 & 0x0) << 5)
#define PLL_RESET_W_MSK (PLL_RESET_MSK << 16)
#define PLL_RESET (1 << 5)
#define PLL_RESET_RESUME (0 << 5)
#define PLL_BYPASS_MSK (1 << 0)
#define PLL_BYPASS (1 << 0)