From 28eb6929be0a0f572324d31b06aa875503bacf22 Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Fri, 24 Dec 2021 01:56:35 +0000 Subject: [PATCH] drm/rockchip: dsi2: set escape clk 10MHz default The Escape clock ranges from 1MHz to 20MHz. Change-Id: I89f8118a4c194cc18f2728968564676e60e4e629 Signed-off-by: Guochun Huang --- drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c index 419de16e6adb..44ce335195b5 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c @@ -547,9 +547,9 @@ static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) */ val |= NON_CONTINUOUS_CLK; - /* The maximum value of the escape clock frequency is 20MHz */ + /* The Escape clock ranges from 1MHz to 20MHz. */ sys_clk = clk_get_rate(dsi2->sys_clk) / USEC_PER_SEC; - esc_clk_div = DIV_ROUND_UP(sys_clk, 20 * 2); + esc_clk_div = DIV_ROUND_UP(sys_clk, 10 * 2); val |= PHY_LPTX_CLK_DIV(esc_clk_div); regmap_write(dsi2->regmap, DSI2_PHY_CLK_CFG, val);