From 29810f8c186330e7d818a702c42a4e459bf40e55 Mon Sep 17 00:00:00 2001 From: Hang Cheng Date: Mon, 11 Nov 2019 15:35:30 +0800 Subject: [PATCH] hdmirx: keep phy para of sm1 consistent with uboot [1/2] PD#SWPL-15262 Problem: flash snow or black screen when switch to 1080p50/60hz rgb,12bit on Sharp LCD-42GX50A Solution: change the phy para according to uboot Verify: U212 board(V2.0) + S905X3 chip Change-Id: If4fadc30aeab51106a11ea861e0ef43b2a5a1318 Signed-off-by: Hang Cheng --- .../vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c | 22 +++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c index fa2612133f75..c9387827770e 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c @@ -1980,10 +1980,20 @@ static void set_phy_by_mode(unsigned int mode) break; case MESON_CPU_ID_SM1: switch (mode) { - case HDMI_PHYPARA_6G: /* 5.94/4.5/3.7Gbps */ - case HDMI_PHYPARA_4p5G: - case HDMI_PHYPARA_3p7G: + case HDMI_PHYPARA_6G: /* 5.94Gbps */ + hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb76d4); + hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); + hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b); + break; + case HDMI_PHYPARA_4p5G: /* 4.5Gbps */ + hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb65d4); + hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); + hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b); + break; + case HDMI_PHYPARA_3p7G: /* 3.7Gbps */ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb65c4); + if (hdev->dongle_mode) + hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb5584); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b); break; @@ -1993,9 +2003,13 @@ static void set_phy_by_mode(unsigned int mode) hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003); break; case HDMI_PHYPARA_270M: /* 1.485Gbps, and below */ + hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb5252); + hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); + hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003); + break; case HDMI_PHYPARA_DEF: default: - hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4242); + hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4262); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003); break;