diff --git a/Documentation/devicetree/bindings/rng/rockchip,rng.txt b/Documentation/devicetree/bindings/rng/rockchip,rng.txt new file mode 100644 index 000000000000..b184cb25113b --- /dev/null +++ b/Documentation/devicetree/bindings/rng/rockchip,rng.txt @@ -0,0 +1,32 @@ +Rockchip Hardware Random Number Generator + +Required properties: + +- compatible : should be one of the following. + "rockchip,cryptov2-rng" for crypto v2 +- reg : Specifies base physical address and size of the registers map. +- clocks : Phandle to clock-controller plus clock-specifier pair. +- clock-names : "clk_crypto", "clk_crypto_apk", "aclk_crypto", "hclk_crypto" as a clock name. +- assigned-clocks: Main clock, should be <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, + <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO> +- assigned-clock-rates : The rng core clk frequency, shall be: <150000000>, <150000000>, + <200000000>, <100000000> +- resets : Used for module reset +- reset-names : Reset names, should be "reset" +Example: + + rng: rng@ff2f0000 { + compatible = "rockchip,cryptov2-rng"; + reg = <0x0 0xff2f0000 0x0 0x4000>; + clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, + <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; + clock-names = "clk_crypto", "clk_crypto_apk", + "aclk_crypto", "hclk_crypto"; + assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, + <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; + assigned-clock-rates = <150000000>, <150000000>, + <200000000>, <100000000>; + resets = <&cru SRST_CRYPTO>; + reset-names = "reset"; + }; +