From 955676e81e80f501344b3a4160956bcb46fe6c07 Mon Sep 17 00:00:00 2001 From: Wang Panzhenzhuan Date: Thu, 27 Jun 2024 09:17:36 +0800 Subject: [PATCH 01/12] arm64: dts: rockchip: rk3399-evb-ind-lpddr4-android: remove unused sgm3784 rk3399-evb-ind board's gpio is not connected to control sgm3784, so remove it Signed-off-by: Wang Panzhenzhuan Change-Id: I6e874c94fc5db82daa3b9f67adc5f5da51731390 --- .../rk3399-evb-ind-lpddr4-v13-android-avb.dts | 26 ------------------- 1 file changed, 26 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb-ind-lpddr4-v13-android-avb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind-lpddr4-v13-android-avb.dts index 0a1dd9c8b40e..0ba611e25240 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-evb-ind-lpddr4-v13-android-avb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind-lpddr4-v13-android-avb.dts @@ -127,31 +127,6 @@ &i2c1 { status = "okay"; - sgm3784: sgm3784@30 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "sgmicro,gsm3784"; - reg = <0x30>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - //enable-gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; - //strobe-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - status = "okay"; - sgm3784_led0: led@0 { - reg = <0x0>; - led-max-microamp = <299200>; - flash-max-microamp = <1122000>; - flash-max-timeout-us = <1600000>; - }; - - sgm3784_led1: led@1 { - reg = <0x1>; - led-max-microamp = <299200>; - flash-max-microamp = <1122000>; - flash-max-timeout-us = <1600000>; - }; - }; - vm149c: vm149c@0c { compatible = "silicon touch,vm149c"; status = "okay"; @@ -205,7 +180,6 @@ rockchip,camera-module-name = "CMK-CT0116"; rockchip,camera-module-lens-name = "Largan-50013A1"; lens-focus = <&vm149c>; - flash-leds = <&sgm3784_led0 &sgm3784_led1>; port { ucam_out0: endpoint { remote-endpoint = <&mipi_in_ucam0>; From 99ada5d52ac6a3f8595f6994e77336ecaf421022 Mon Sep 17 00:00:00 2001 From: Wang Panzhenzhuan Date: Wed, 26 Jun 2024 17:58:10 +0800 Subject: [PATCH 02/12] media: i2c: vm149c: fix compile error Signed-off-by: Wang Panzhenzhuan Change-Id: I12cb08d62125eedafe6a37505e76d14e2a0cd6c7 --- drivers/media/i2c/Kconfig | 11 +++++++++++ drivers/media/i2c/Makefile | 1 + drivers/media/i2c/vm149c.c | 17 +++++++++++------ 3 files changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 17faed1c240f..827ce8805568 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -2196,6 +2196,17 @@ config VIDEO_FP5510 capability. This is designed for linear control of voice coil motors, controlled via I2C serial interface. +config VIDEO_VM149C + tristate "VM149C lens voice coil support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + help + This is a driver for the VM149C camera lens voice coil. + VM149C is a 10 bit DAC with 100mA output current sink + capability. This is designed for linear control of + voice coil motors, controlled via I2C serial interface. + endmenu menu "Flash devices" diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index a3e02912f846..284a2390dea9 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -281,6 +281,7 @@ obj-$(CONFIG_VIDEO_TW9910) += tw9910.o obj-$(CONFIG_VIDEO_UDA1342) += uda1342.o obj-$(CONFIG_VIDEO_UPD64031A) += upd64031a.o obj-$(CONFIG_VIDEO_UPD64083) += upd64083.o +obj-$(CONFIG_VIDEO_VM149C) += vm149c.o obj-$(CONFIG_VIDEO_VP27SMPX) += vp27smpx.o obj-$(CONFIG_VIDEO_VPX3220) += vpx3220.o obj-$(CONFIG_VIDEO_VS6624) += vs6624.o diff --git a/drivers/media/i2c/vm149c.c b/drivers/media/i2c/vm149c.c index b73f628e85ea..18c24cfecf4e 100644 --- a/drivers/media/i2c/vm149c.c +++ b/drivers/media/i2c/vm149c.c @@ -36,8 +36,8 @@ struct vm149c_device { unsigned int step_mode; unsigned int vcm_movefull_t; - struct timeval start_move_tv; - struct timeval end_move_tv; + struct __kernel_old_timeval start_move_tv; + struct __kernel_old_timeval end_move_tv; unsigned long move_ms; u32 module_index; @@ -251,7 +251,7 @@ static int vm149c_set_ctrl(struct v4l2_ctrl *ctrl) dev_dbg(&client->dev, "dest_pos %d, move_ms %ld\n", dest_pos, dev_vcm->move_ms); - dev_vcm->start_move_tv = ns_to_timeval(ktime_get_ns()); + dev_vcm->start_move_tv = ns_to_kernel_old_timeval(ktime_get_ns()); mv_us = dev_vcm->start_move_tv.tv_usec + dev_vcm->move_ms * 1000; if (mv_us >= 1000000) { @@ -389,12 +389,17 @@ static long vm149c_compat_ioctl32(struct v4l2_subdev *sd, unsigned int cmd, unsi put_user(compat_vcm_tim.vcm_end_t.tv_usec, &p32->vcm_end_t.tv_usec); } else if (cmd == RK_VIDIOC_GET_VCM_CFG) { ret = vm149c_ioctl(sd, RK_VIDIOC_GET_VCM_CFG, &vcm_cfg); - if (!ret) + if (!ret) { ret = copy_to_user(up, &vcm_cfg, sizeof(vcm_cfg)); + if (ret) + ret = -EFAULT; + } } else if (cmd == RK_VIDIOC_SET_VCM_CFG) { ret = copy_from_user(&vcm_cfg, up, sizeof(vcm_cfg)); if (!ret) ret = vm149c_ioctl(sd, cmd, &vcm_cfg); + else + ret = -EFAULT; } else { dev_err(&client->dev, "cmd 0x%x not supported\n", cmd); @@ -543,8 +548,8 @@ static int vm149c_probe(struct i2c_client *client, vm149c_update_vcm_cfg(vm149c_dev); vm149c_dev->move_ms = 0; vm149c_dev->current_related_pos = VCMDRV_MAX_LOG; - vm149c_dev->start_move_tv = ns_to_timeval(ktime_get_ns()); - vm149c_dev->end_move_tv = ns_to_timeval(ktime_get_ns()); + vm149c_dev->start_move_tv = ns_to_kernel_old_timeval(ktime_get_ns()); + vm149c_dev->end_move_tv = ns_to_kernel_old_timeval(ktime_get_ns()); if ((vm149c_dev->step_mode & 0x0c) != 0) { vm149c_dev->vcm_movefull_t = 64 * (1 << (vm149c_dev->step_mode & 0x03)) * 1024 / From ad3c91351d647c1aea70a968e276e4ec029b5aa6 Mon Sep 17 00:00:00 2001 From: Wang Panzhenzhuan Date: Wed, 23 Feb 2022 14:29:44 +0800 Subject: [PATCH 03/12] arm64: dts: rockchip: rk3399-evb-ind-lpddr4-android: add gc8034 config Signed-off-by: Wang Panzhenzhuan Change-Id: I99e44cd0212e2a7d3a3e74ec528dae379f3930b5 --- .../rk3399-evb-ind-lpddr4-android-avb.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb-ind-lpddr4-android-avb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind-lpddr4-android-avb.dts index d59bb9397307..bde1d3fb5683 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-evb-ind-lpddr4-android-avb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind-lpddr4-android-avb.dts @@ -149,6 +149,29 @@ rockchip,camera-module-facing = "back"; }; + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "LH-RK-8034-v1.0"; + rockchip,camera-module-lens-name = "CK8401"; + lens-focus = <&vm149c>; + port { + gc8034_out: endpoint { + remote-endpoint = <&mipi_in_gc8034>; + data-lanes = <1 2 3 4>; + }; + }; + }; + gc2145: gc2145@3c{ status = "okay"; compatible = "galaxycore,gc2145"; @@ -286,6 +309,11 @@ #address-cells = <1>; #size-cells = <0>; + mipi_in_gc8034: endpoint@0 { + reg = <0>; + remote-endpoint = <&gc8034_out>; + data-lanes = <1 2 3 4>; + }; mipi_in_ucam0: endpoint@1 { reg = <1>; remote-endpoint = <&ucam_out0>; From 70fc302a5b7eaae7be49e6322591a6ee1a362889 Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Tue, 25 Jun 2024 15:00:10 +0800 Subject: [PATCH 04/12] drm/rockchip: dw-hdmi-qp: Fix hpd irq mute after resume Change-Id: I027005f7978b8a2e2f8e2eada97b7f6e6a0adb18 Signed-off-by: Algea Cao --- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c index d067d3ccd6e8..e91379fef9fa 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -4277,6 +4277,9 @@ void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi) mutex_unlock(&hdmi->mutex); + if (hdmi->phy.ops->setup_hpd) + hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); + result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); if (result == connector_status_connected) { mutex_lock(&hdmi->connector.dev->mode_config.mutex); From 85ebb3a26dd446a19b321f15fc6872278ed8dd01 Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Tue, 25 Jun 2024 15:03:12 +0800 Subject: [PATCH 05/12] drm/rockchip: dw-hdmi-qp: Fix crash caused by excessive memory usage when resume Each time edid is parsed, all resolutions are added to connector->probed_modes. drm_connector_list_update() must be called, it will remove useless modes. Otherwise connector->probed_modes will continue to expand. Change-Id: Ie61db721fa34e1cabc20209d87273e1b578ed36f Signed-off-by: Algea Cao --- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c index e91379fef9fa..467081841bc8 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -4283,7 +4283,7 @@ void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi) result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); if (result == connector_status_connected) { mutex_lock(&hdmi->connector.dev->mode_config.mutex); - dw_hdmi_connector_get_modes(&hdmi->connector); + drm_helper_probe_single_connector_modes(&hdmi->connector, 9000, 9000); mutex_unlock(&hdmi->connector.dev->mode_config.mutex); } } From 238ecdec050238194f8059c6e8a850c3c7fbfb84 Mon Sep 17 00:00:00 2001 From: Yifeng Zhao Date: Mon, 8 Apr 2024 10:56:18 +0800 Subject: [PATCH 06/12] scsi: ufs: rockchip: modify MPHY configuration based on signal testing Signed-off-by: Yifeng Zhao Change-Id: I6ec2bbf2e33279c3451ff91a55a8312da6d1c4c5 --- drivers/ufs/host/ufs-rockchip.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/ufs/host/ufs-rockchip.c b/drivers/ufs/host/ufs-rockchip.c index b1669d3746f0..b1c7d8d89c90 100644 --- a/drivers/ufs/host/ufs-rockchip.c +++ b/drivers/ufs/host/ufs-rockchip.c @@ -306,6 +306,12 @@ static int ufs_rockchip_rk3576_phy_init(struct ufs_hba *hba) ufs_sys_writel(host->mphy_base, 0x18, 0x1B0); ufs_sys_writel(host->mphy_base, 0x18, 0x2F0); + ufs_sys_writel(host->mphy_base, 0x03, 0x128); + ufs_sys_writel(host->mphy_base, 0x03, 0x268); + + ufs_sys_writel(host->mphy_base, 0x20, 0x12C); + ufs_sys_writel(host->mphy_base, 0x20, 0x26C); + ufs_sys_writel(host->mphy_base, 0xC0, 0x120); ufs_sys_writel(host->mphy_base, 0xC0, 0x260); From a89ecfeca2f0843649674a57c68b0e61dc34c4c5 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 21 Jun 2024 15:58:51 +0800 Subject: [PATCH 07/12] arm64: dts: rockchip: rk3576: Change ddr and logic voltage Signed-off-by: Finley Xiao Change-Id: I20010a5874130865989f61bb58f1f581cc4af107 --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 52 +++++++++++++++--------- 1 file changed, 33 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 98881632506c..034f1a73890b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -827,35 +827,44 @@ rockchip,low-temp-min-volt = <750000>; rockchip,leakage-voltage-sel = < - 1 16 0 - 17 254 1 + 1 10 0 + 11 20 1 + 21 254 2 >; opp-528000000 { opp-hz = /bits/ 64 <528000000>; - opp-microvolt = <725000 725000 850000>, - <725000 725000 800000>; - opp-microvolt-L1 = <700000 700000 850000>, - <700000 700000 800000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 800000>; + opp-microvolt-L1 = <725000 725000 850000>, + <725000 725000 800000>; + opp-microvolt-L2 = <712500 712500 850000>, + <712500 712500 800000>; }; opp-1068000000 { opp-hz = /bits/ 64 <1068000000>; - opp-microvolt = <725000 725000 850000>, - <725000 725000 800000>; - opp-microvolt-L1 = <700000 700000 850000>, - <700000 700000 800000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 800000>; + opp-microvolt-L1 = <725000 725000 850000>, + <725000 725000 800000>; + opp-microvolt-L2 = <712500 712500 850000>, + <712500 712500 800000>; }; opp-1560000000 { opp-hz = /bits/ 64 <1560000000>; - opp-microvolt = <725000 725000 850000>, - <725000 725000 800000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 800000>; opp-microvolt-L1 = <725000 725000 850000>, <725000 725000 800000>; + opp-microvolt-L2 = <725000 725000 850000>, + <725000 725000 800000>; }; opp-2736000000 { opp-hz = /bits/ 64 <2736000000>; - opp-microvolt = <800000 800000 850000>, + opp-microvolt = <825000 825000 850000>, <750000 750000 800000>; - opp-microvolt-L1 = <775000 775000 850000>, + opp-microvolt-L1 = <800000 800000 850000>, + <725000 725000 800000>; + opp-microvolt-L2 = <775000 775000 850000>, <725000 725000 800000>; }; }; @@ -2925,22 +2934,27 @@ rockchip,init-freq = <702000>; /* KHz */ rockchip,leakage-voltage-sel = < - 1 16 0 - 17 254 1 + 1 10 0 + 11 20 1 + 21 254 2 >; opp-500000000 { opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <700000 700000 800000>; + opp-microvolt = <725000 725000 800000>; + opp-microvolt-L1 = <712500 712500 800000>; + opp-microvolt-L2 = <712500 712500 800000>; }; opp-594000000 { opp-hz = /bits/ 64 <594000000>; opp-microvolt = <750000 750000 800000>; - opp-microvolt-L1 = <725000 725000 800000>; + opp-microvolt-L1 = <750000 750000 800000>; + opp-microvolt-L2 = <725000 725000 800000>; }; opp-702000000 { opp-hz = /bits/ 64 <702000000>; opp-microvolt = <750000 750000 800000>; - opp-microvolt-L1 = <725000 725000 800000>; + opp-microvolt-L1 = <750000 750000 800000>; + opp-microvolt-L2 = <725000 725000 800000>; }; }; From 404d56f2e02fac265c05a890f9fa52f8a9a8c742 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 21 Jun 2024 17:06:28 +0800 Subject: [PATCH 08/12] soc: rockchip: opp_select: Implement rockchip_opp_set_low_length() Signed-off-by: Finley Xiao Change-Id: I17b57fe52bd764deec1400c88ac49a24b25ccaeb --- drivers/soc/rockchip/rockchip_opp_select.c | 40 ++++++++++++++++++++++ include/soc/rockchip/rockchip_opp_select.h | 9 +++++ 2 files changed, 49 insertions(+) diff --git a/drivers/soc/rockchip/rockchip_opp_select.c b/drivers/soc/rockchip/rockchip_opp_select.c index 842589fb7083..246e1460a7a1 100644 --- a/drivers/soc/rockchip/rockchip_opp_select.c +++ b/drivers/soc/rockchip/rockchip_opp_select.c @@ -2202,6 +2202,46 @@ int rockchip_set_intermediate_rate(struct device *dev, } EXPORT_SYMBOL(rockchip_set_intermediate_rate); +int rockchip_opp_set_low_length(struct device *dev, struct device_node *np, + struct rockchip_opp_info *opp_info) +{ + struct clk *clk; + unsigned long old_rate; + unsigned int low_len_sel; + u32 opp_flag = 0; + int ret = 0; + + if (opp_info->volt_sel < 0) + return 0; + + clk = clk_get(dev, NULL); + if (IS_ERR(clk)) { + dev_warn(dev, "failed to get cpu clk\n"); + return PTR_ERR(clk); + } + + /* low speed grade should change to low length */ + if (of_property_read_u32(np, "rockchip,pvtm-low-len-sel", + &low_len_sel)) + goto out; + if (opp_info->volt_sel > low_len_sel) + goto out; + opp_flag = OPP_LENGTH_LOW; + + old_rate = clk_get_rate(clk); + ret = clk_set_rate(clk, old_rate | opp_flag); + if (ret) { + dev_err(dev, "failed to change length\n"); + goto out; + } + clk_set_rate(clk, old_rate); +out: + clk_put(clk); + + return ret; +} +EXPORT_SYMBOL(rockchip_opp_set_low_length); + static int rockchip_opp_set_volt(struct device *dev, struct regulator *reg, struct dev_pm_opp_supply *supply, char *reg_name) { diff --git a/include/soc/rockchip/rockchip_opp_select.h b/include/soc/rockchip/rockchip_opp_select.h index c8355ff46d25..f448b3814508 100644 --- a/include/soc/rockchip/rockchip_opp_select.h +++ b/include/soc/rockchip/rockchip_opp_select.h @@ -166,6 +166,8 @@ int rockchip_set_intermediate_rate(struct device *dev, struct clk *clk, unsigned long old_freq, unsigned long new_freq, bool is_scaling_up, bool is_set_clk); +int rockchip_opp_set_low_length(struct device *dev, struct device_node *np, + struct rockchip_opp_info *opp_info); int rockchip_opp_config_regulators(struct device *dev, struct dev_pm_opp *old_opp, struct dev_pm_opp *new_opp, @@ -253,6 +255,13 @@ rockchip_set_intermediate_rate(struct device *dev, return -EOPNOTSUPP; } +static inline int +rockchip_opp_set_low_length(struct device *dev, struct device_node *np, + struct rockchip_opp_info *opp_info) +{ + return -EOPNOTSUPP; +} + static inline int rockchip_opp_config_regulators(struct device *dev, struct dev_pm_opp *old_opp, From 0af1954a8d157d5decf27b3e365d11ac9e279597 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 21 Jun 2024 17:08:16 +0800 Subject: [PATCH 09/12] cpufreq: rockchip: Add set soc info for rk3576 Signed-off-by: Finley Xiao Change-Id: Ifbaa8d8f2f40ef1828e3844e8e9897ab65eda92e --- drivers/cpufreq/rockchip-cpufreq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/rockchip-cpufreq.c b/drivers/cpufreq/rockchip-cpufreq.c index a1fc6d8ad497..5a6c555ae41a 100644 --- a/drivers/cpufreq/rockchip-cpufreq.c +++ b/drivers/cpufreq/rockchip-cpufreq.c @@ -408,6 +408,7 @@ static const struct rockchip_opp_data rk3588_cpu_opp_data = { static const struct rockchip_opp_data rk3576_cpu_opp_data = { .set_read_margin = rk3576_cpu_set_read_margin, + .set_soc_info = rockchip_opp_set_low_length, .config_regulators = cpu_opp_config_regulators, }; From a911fef70d784bed72365c05a65c4485f3b5060a Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 21 Jun 2024 17:18:23 +0800 Subject: [PATCH 10/12] driver: rknpu: Add set soc info for rk3576 Signed-off-by: Finley Xiao Change-Id: Ifc31a47c9c75e72ea2cc09fcd2c1a70ab664d1c8 --- drivers/rknpu/rknpu_devfreq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/rknpu/rknpu_devfreq.c b/drivers/rknpu/rknpu_devfreq.c index 2668d2c4666e..c6a553d9b846 100644 --- a/drivers/rknpu/rknpu_devfreq.c +++ b/drivers/rknpu/rknpu_devfreq.c @@ -234,6 +234,7 @@ static int npu_opp_config_clks(struct device *dev, struct opp_table *opp_table, static const struct rockchip_opp_data rk3576_npu_opp_data = { .set_read_margin = rk3576_npu_set_read_margin, + .set_soc_info = rockchip_opp_set_low_length, #if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE .config_regulators = npu_opp_config_regulators, .config_clks = npu_opp_config_clks, From b7e25db5d01c77cd071ef22f56502a94fe472f6d Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 21 Jun 2024 17:20:14 +0800 Subject: [PATCH 11/12] MALI: bifrost: Add set soc info for rk3576 Signed-off-by: Finley Xiao Change-Id: I6d6d617a0be67c80e6119fcb291710161497b187 --- drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c b/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c index a9176d427ad9..07b300651b02 100755 --- a/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c +++ b/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c @@ -647,6 +647,7 @@ static int gpu_opp_config_clks(struct device *dev, struct opp_table *opp_table, static const struct rockchip_opp_data rk3576_gpu_opp_data = { .set_read_margin = rk3576_gpu_set_read_margin, + .set_soc_info = rockchip_opp_set_low_length, .config_regulators = gpu_opp_config_regulators, .config_clks = gpu_opp_config_clks, }; From b04747085f2f8f9375e834adfa48a547fa920309 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 21 Jun 2024 17:26:31 +0800 Subject: [PATCH 12/12] arm64: dts: rockchip: rk3576: Change opp table for cpu gpu and npu Signed-off-by: Finley Xiao Change-Id: I433b5b8189fb542a5a73298f4db80ed40e5131a6 --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 370 ++++++++++++++--------- 1 file changed, 223 insertions(+), 147 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 034f1a73890b..a1633911a4af 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -398,12 +398,17 @@ nvmem-cell-names = "leakage", "opp-info"; rockchip,pvtm-voltage-sel = < - 0 1939 0 - 1940 1969 1 - 1970 1999 2 - 2000 2029 3 - 2030 2059 4 - 2060 9999 5 + 0 1764 0 + 1765 1789 1 + 1790 1819 2 + 1820 1854 3 + 1855 1889 4 + 1890 1924 5 + 1925 1959 6 + 1960 1999 7 + 2000 2039 8 + 2040 2079 9 + 2080 9999 10 >; rockchip,pvtm-pvtpll; rockchip,pvtpll = <&litcore_pvtpll>; @@ -433,78 +438,87 @@ opp-408000000 { opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <700000 700000 950000>; + opp-microvolt = <712500 712500 950000>; clock-latency-ns = <40000>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <700000 700000 950000>; + opp-microvolt = <712500 712500 950000>; clock-latency-ns = <40000>; }; opp-816000000 { opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <700000 700000 950000>; + opp-microvolt = <712500 712500 950000>; clock-latency-ns = <40000>; }; opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <700000 700000 950000>; + opp-microvolt = <712500 712500 950000>; + opp-microvolt-L0 = <725000 725000 950000>; clock-latency-ns = <40000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <700000 700000 950000>; + opp-microvolt = <712500 712500 950000>; + opp-microvolt-L0 = <737500 737500 950000>; + opp-microvolt-L1 = <725000 725000 950000>; clock-latency-ns = <40000>; }; opp-1416000000 { opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <725000 725000 950000>; - opp-microvolt-L1 = <712500 712500 950000>; - opp-microvolt-L2 = <700000 700000 950000>; - opp-microvolt-L3 = <700000 700000 950000>; - opp-microvolt-L4 = <700000 700000 950000>; - opp-microvolt-L5 = <700000 700000 950000>; + opp-microvolt = <712500 712500 950000>; + opp-microvolt-L0 = <775000 775000 950000>; + opp-microvolt-L1 = <762500 762500 950000>; + opp-microvolt-L2 = <750000 750000 950000>; + opp-microvolt-L3 = <750000 750000 950000>; + opp-microvolt-L4 = <737500 737500 950000>; + opp-microvolt-L5 = <725000 725000 950000>; clock-latency-ns = <40000>; }; opp-1608000000 { opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <750000 750000 950000>; - opp-microvolt-L1 = <750000 750000 950000>; - opp-microvolt-L2 = <737500 737500 950000>; - opp-microvolt-L3 = <737500 737500 950000>; - opp-microvolt-L4 = <725000 725000 950000>; - opp-microvolt-L5 = <712500 712500 950000>; + opp-microvolt = <812500 812500 950000>; + opp-microvolt-L1 = <800000 800000 950000>; + opp-microvolt-L2 = <787500 787500 950000>; + opp-microvolt-L3 = <787500 787500 950000>; + opp-microvolt-L4 = <775000 775000 950000>; + opp-microvolt-L5 = <762500 762500 950000>; + opp-microvolt-L6 = <750000 750000 950000>; + opp-microvolt-L7 = <737500 737500 950000>; + opp-microvolt-L8 = <725000 725000 950000>; + opp-microvolt-L9 = <725000 725000 950000>; + opp-microvolt-L10 = <712500 712500 950000>; clock-latency-ns = <40000>; }; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <825000 825000 950000>; - opp-microvolt-L1 = <825000 825000 950000>; - opp-microvolt-L2 = <812500 812500 950000>; - opp-microvolt-L3 = <800000 800000 950000>; - opp-microvolt-L4 = <787500 787500 950000>; - opp-microvolt-L5 = <775000 775000 950000>; + opp-microvolt = <887500 887500 950000>; + opp-microvolt-L1 = <875000 875000 950000>; + opp-microvolt-L2 = <862500 862500 950000>; + opp-microvolt-L3 = <850000 850000 950000>; + opp-microvolt-L4 = <837500 837500 950000>; + opp-microvolt-L5 = <825000 825000 950000>; + opp-microvolt-L6 = <812500 812500 950000>; + opp-microvolt-L7 = <800000 800000 950000>; + opp-microvolt-L8 = <787500 787500 950000>; + opp-microvolt-L9 = <775000 775000 950000>; + opp-microvolt-L10 = <762500 762500 950000>; clock-latency-ns = <40000>; opp-suspend; }; opp-2016000000 { opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <900000 900000 950000>; - opp-microvolt-L1 = <887500 887500 950000>; - opp-microvolt-L2 = <875000 875000 950000>; - opp-microvolt-L3 = <862500 862500 950000>; - opp-microvolt-L4 = <850000 850000 950000>; - opp-microvolt-L5 = <837500 837500 950000>; - clock-latency-ns = <40000>; - }; - opp-2208000000 { - opp-hz = /bits/ 64 <2208000000>; opp-microvolt = <950000 950000 950000>; opp-microvolt-L1 = <937500 937500 950000>; opp-microvolt-L2 = <925000 925000 950000>; opp-microvolt-L3 = <912500 912500 950000>; opp-microvolt-L4 = <900000 900000 950000>; opp-microvolt-L5 = <887500 887500 950000>; + opp-microvolt-L6 = <875000 875000 950000>; + opp-microvolt-L7 = <862500 862500 950000>; + opp-microvolt-L8 = <850000 850000 950000>; + opp-microvolt-L9 = <837500 837500 950000>; + opp-microvolt-L10 = <825000 825000 950000>; clock-latency-ns = <40000>; }; }; @@ -518,13 +532,19 @@ nvmem-cell-names = "leakage", "opp-info"; rockchip,pvtm-voltage-sel = < - 0 2065 0 - 2066 2095 1 - 2096 2125 2 - 2126 2155 3 - 2156 2185 4 - 2186 9999 5 + 0 1919 0 + 1920 1949 1 + 1950 1979 2 + 1980 2009 3 + 2010 2049 4 + 2050 2089 5 + 2090 2129 6 + 2130 2169 7 + 2170 2209 8 + 2210 2249 9 + 2250 9999 10 >; + rockchip,pvtm-low-len-sel = <0>; rockchip,pvtm-pvtpll; rockchip,pvtpll = <&bigcore_pvtpll>; rockchip,pvtm-offset = <0x54>; @@ -552,88 +572,96 @@ opp-408000000 { opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <700000 700000 950000>; + opp-microvolt = <712500 712500 950000>; clock-latency-ns = <40000>; opp-suspend; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <700000 700000 950000>; + opp-microvolt = <712500 712500 950000>; clock-latency-ns = <40000>; }; opp-816000000 { opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <700000 700000 950000>; + opp-microvolt = <712500 712500 950000>; clock-latency-ns = <40000>; }; opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <700000 700000 950000>; + opp-microvolt = <712500 712500 950000>; clock-latency-ns = <40000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <700000 700000 950000>; + opp-microvolt = <712500 712500 950000>; + opp-microvolt-L0 = <750000 750000 950000>; + opp-microvolt-L1 = <750000 750000 950000>; + opp-microvolt-L2 = <737500 737500 950000>; + opp-microvolt-L3 = <725000 725000 950000>; clock-latency-ns = <40000>; }; opp-1416000000 { opp-hz = /bits/ 64 <1416000000>; opp-microvolt = <712500 712500 950000>; - opp-microvolt-L1 = <700000 700000 950000>; - opp-microvolt-L2 = <700000 700000 950000>; - opp-microvolt-L3 = <700000 700000 950000>; - opp-microvolt-L4 = <700000 700000 950000>; - opp-microvolt-L5 = <700000 700000 950000>; + opp-microvolt-L0 = <750000 750000 950000>; + opp-microvolt-L1 = <750000 750000 950000>; + opp-microvolt-L2 = <737500 737500 950000>; + opp-microvolt-L3 = <725000 725000 950000>; clock-latency-ns = <40000>; }; opp-1608000000 { opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <737500 737500 950000>; - opp-microvolt-L1 = <725000 725000 950000>; - opp-microvolt-L2 = <712500 712500 950000>; - opp-microvolt-L3 = <700000 700000 950000>; - opp-microvolt-L4 = <700000 700000 950000>; - opp-microvolt-L5 = <700000 700000 950000>; + opp-microvolt = <725000 725000 950000>; + opp-microvolt-L0 = <775000 775000 950000>; + opp-microvolt-L1 = <775000 775000 950000>; + opp-microvolt-L2 = <762500 762500 950000>; + opp-microvolt-L3 = <750000 750000 950000>; + opp-microvolt-L4 = <737500 737500 950000>; clock-latency-ns = <40000>; }; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <800000 800000 950000>; - opp-microvolt-L1 = <787500 787500 950000>; - opp-microvolt-L2 = <775000 775000 950000>; - opp-microvolt-L3 = <762500 762500 950000>; - opp-microvolt-L4 = <750000 750000 950000>; - opp-microvolt-L5 = <737500 737500 950000>; + opp-microvolt = <825000 825000 950000>; + opp-microvolt-L1 = <825000 825000 950000>; + opp-microvolt-L2 = <812500 812500 950000>; + opp-microvolt-L3 = <800000 800000 950000>; + opp-microvolt-L4 = <787500 787500 950000>; + opp-microvolt-L5 = <775000 775000 950000>; + opp-microvolt-L6 = <762500 762500 950000>; + opp-microvolt-L7 = <750000 750000 950000>; + opp-microvolt-L8 = <737500 737500 950000>; + opp-microvolt-L9 = <725000 725000 950000>; + opp-microvolt-L10 = <725000 725000 950000>; clock-latency-ns = <40000>; }; opp-2016000000 { opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <862500 862500 950000>; - opp-microvolt-L1 = <850000 850000 950000>; - opp-microvolt-L2 = <837500 837500 950000>; - opp-microvolt-L3 = <825000 825000 950000>; - opp-microvolt-L4 = <812500 812500 950000>; - opp-microvolt-L5 = <800000 800000 950000>; + opp-microvolt = <887500 887500 950000>; + opp-microvolt-L1 = <887500 887500 950000>; + opp-microvolt-L2 = <875000 875000 950000>; + opp-microvolt-L3 = <862500 862500 950000>; + opp-microvolt-L4 = <850000 850000 950000>; + opp-microvolt-L5 = <837500 837500 950000>; + opp-microvolt-L6 = <825000 825000 950000>; + opp-microvolt-L7 = <812500 812500 950000>; + opp-microvolt-L8 = <800000 800000 950000>; + opp-microvolt-L9 = <787500 787500 950000>; + opp-microvolt-L10 = <775000 775000 950000>; clock-latency-ns = <40000>; }; opp-2208000000 { opp-hz = /bits/ 64 <2208000000>; - opp-microvolt = <925000 925000 950000>; - opp-microvolt-L1 = <912500 912500 950000>; - opp-microvolt-L2 = <900000 900000 950000>; - opp-microvolt-L3 = <887500 887500 950000>; - opp-microvolt-L4 = <875000 875000 950000>; - opp-microvolt-L5 = <862500 862500 950000>; - clock-latency-ns = <40000>; - }; - opp-2304000000 { - opp-hz = /bits/ 64 <2304000000>; opp-microvolt = <950000 950000 950000>; - opp-microvolt-L1 = <937500 937500 950000>; - opp-microvolt-L2 = <925000 925000 950000>; - opp-microvolt-L3 = <912500 912500 950000>; - opp-microvolt-L4 = <900000 900000 950000>; - opp-microvolt-L5 = <887500 887500 950000>; + opp-microvolt-L1 = <950000 950000 950000>; + opp-microvolt-L2 = <937500 937500 950000>; + opp-microvolt-L3 = <925000 925000 950000>; + opp-microvolt-L4 = <912500 912500 950000>; + opp-microvolt-L5 = <900000 900000 950000>; + opp-microvolt-L6 = <887500 887500 950000>; + opp-microvolt-L7 = <875000 875000 950000>; + opp-microvolt-L8 = <862500 862500 950000>; + opp-microvolt-L9 = <850000 850000 950000>; + opp-microvolt-L10 = <837500 837500 950000>; clock-latency-ns = <40000>; }; }; @@ -2042,12 +2070,19 @@ nvmem-cell-names = "leakage", "opp-info"; rockchip,pvtm-voltage-sel = < - 0 796 0 - 797 816 1 - 817 836 2 - 837 856 3 - 857 9999 4 + 0 719 0 + 720 739 1 + 740 759 2 + 760 779 3 + 780 799 4 + 800 819 5 + 820 839 6 + 840 859 7 + 860 879 8 + 880 899 9 + 900 9999 10 >; + rockchip,pvtm-low-len-sel = <0>; rockchip,pvtm-pvtpll; rockchip,pvtpll = <&npu_pvtpll>; rockchip,pvtm-offset = <0x54>; @@ -2076,49 +2111,76 @@ opp-300000000 { opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <725000 725000 850000>; + opp-microvolt = <725000 725000 875000>; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <725000 725000 850000>; + opp-microvolt = <725000 725000 875000>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <725000 725000 850000>; + opp-microvolt = <725000 725000 875000>; + opp-microvolt-L0 = <737500 737500 875000>; + opp-microvolt-L1 = <737500 737500 875000>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <725000 725000 850000>; + opp-microvolt = <725000 725000 875000>; + opp-microvolt-L0 = <737500 737500 875000>; + opp-microvolt-L1 = <737500 737500 875000>; }; opp-700000000 { opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <750000 750000 850000>; - opp-microvolt-L1 = <737500 737500 850000>; - opp-microvolt-L2 = <725000 725000 850000>; - opp-microvolt-L3 = <725000 725000 850000>; - opp-microvolt-L4 = <725000 725000 850000>; + opp-microvolt = <725000 725000 875000>; + opp-microvolt-L0 = <775000 775000 875000>; + opp-microvolt-L1 = <775000 775000 875000>; + opp-microvolt-L2 = <762500 762500 875000>; + opp-microvolt-L3 = <762500 762500 875000>; + opp-microvolt-L4 = <750000 750000 875000>; + opp-microvolt-L5 = <737500 737500 875000>; + opp-microvolt-L6 = <725000 725000 875000>; }; opp-800000000 { opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <775000 775000 850000>; - opp-microvolt-L1 = <762500 762500 850000>; - opp-microvolt-L2 = <750000 750000 850000>; - opp-microvolt-L3 = <737500 737500 850000>; - opp-microvolt-L4 = <725000 725000 850000>; + opp-microvolt = <800000 800000 875000>; + opp-microvolt-L1 = <800000 800000 875000>; + opp-microvolt-L2 = <787500 787500 875000>; + opp-microvolt-L3 = <775000 775000 875000>; + opp-microvolt-L4 = <762500 762500 875000>; + opp-microvolt-L5 = <750000 750000 875000>; + opp-microvolt-L6 = <737500 737500 875000>; + opp-microvolt-L7 = <725000 725000 875000>; + opp-microvolt-L8 = <725000 725000 875000>; + opp-microvolt-L9 = <725000 725000 875000>; + opp-microvolt-L10 = <725000 725000 875000>; }; opp-900000000 { opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <800000 800000 850000>; - opp-microvolt-L1 = <787500 787500 850000>; - opp-microvolt-L2 = <775000 775000 850000>; - opp-microvolt-L3 = <762500 762500 850000>; - opp-microvolt-L4 = <750000 750000 850000>; + opp-microvolt = <850000 850000 875000>; + opp-microvolt-L1 = <850000 850000 875000>; + opp-microvolt-L2 = <837500 837500 875000>; + opp-microvolt-L3 = <825000 825000 875000>; + opp-microvolt-L4 = <812500 812500 875000>; + opp-microvolt-L5 = <800000 800000 875000>; + opp-microvolt-L6 = <787500 787500 875000>; + opp-microvolt-L7 = <775000 775000 875000>; + opp-microvolt-L8 = <762500 762500 875000>; + opp-microvolt-L9 = <750000 750000 875000>; + opp-microvolt-L10 = <737500 737500 875000>; }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <850000 850000 850000>; - opp-microvolt-L3 = <837500 837500 850000>; - opp-microvolt-L4 = <825000 825000 850000>; + opp-950000000 { + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <875000 875000 875000>; + opp-microvolt-L1 = <875000 875000 875000>; + opp-microvolt-L2 = <862500 862500 875000>; + opp-microvolt-L3 = <850000 850000 875000>; + opp-microvolt-L4 = <837500 837500 875000>; + opp-microvolt-L5 = <825000 825000 875000>; + opp-microvolt-L6 = <812500 812500 875000>; + opp-microvolt-L7 = <800000 800000 875000>; + opp-microvolt-L8 = <787500 787500 875000>; + opp-microvolt-L9 = <775000 775000 875000>; + opp-microvolt-L10 = <762500 762500 875000>; }; }; @@ -2167,12 +2229,19 @@ nvmem-cell-names = "leakage", "opp-info"; rockchip,pvtm-voltage-sel = < - 0 800 0 - 801 820 1 - 821 840 2 - 841 860 3 - 861 9999 4 + 0 704 0 + 705 724 1 + 725 744 2 + 745 764 3 + 765 784 4 + 785 804 5 + 805 824 6 + 825 844 7 + 845 864 8 + 865 884 9 + 885 9999 10 >; + rockchip,pvtm-low-len-sel = <0>; rockchip,pvtm-pvtpll; rockchip,pvtpll = <&gpu_pvtpll>; rockchip,pvtm-offset = <0x54>; @@ -2199,49 +2268,56 @@ opp-300000000 { opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <700000 700000 850000>; + opp-microvolt = <712500 712500 875000>; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <700000 700000 850000>; + opp-microvolt = <712500 712500 875000>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <700000 700000 850000>; + opp-microvolt = <712500 712500 875000>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <700000 700000 850000>; + opp-microvolt = <712500 712500 875000>; }; opp-700000000 { opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <725000 725000 850000>; - opp-microvolt-L1 = <712500 712500 850000>; - opp-microvolt-L2 = <700000 700000 850000>; - opp-microvolt-L3 = <700000 700000 850000>; - opp-microvolt-L4 = <700000 700000 850000>; + opp-microvolt = <712500 712500 875000>; + opp-microvolt-L0 = <750000 750000 875000>; + opp-microvolt-L1 = <750000 750000 875000>; + opp-microvolt-L2 = <737500 737500 875000>; + opp-microvolt-L3 = <725000 725000 875000>; + opp-microvolt-L4 = <725000 725000 875000>; }; opp-800000000 { opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <775000 775000 850000>; - opp-microvolt-L1 = <762500 762500 850000>; - opp-microvolt-L2 = <750000 750000 850000>; - opp-microvolt-L3 = <737500 737500 850000>; - opp-microvolt-L4 = <725000 725000 850000>; + opp-microvolt = <812500 812500 875000>; + opp-microvolt-L1 = <812500 812500 875000>; + opp-microvolt-L2 = <800000 800000 875000>; + opp-microvolt-L3 = <787500 787500 875000>; + opp-microvolt-L4 = <775000 775000 875000>; + opp-microvolt-L5 = <762500 762500 875000>; + opp-microvolt-L6 = <750000 750000 875000>; + opp-microvolt-L7 = <737500 737500 875000>; + opp-microvolt-L8 = <725000 725000 875000>; + opp-microvolt-L9 = <725000 725000 875000>; + opp-microvolt-L10 = <725000 725000 875000>; }; opp-900000000 { opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <825000 825000 850000>; - opp-microvolt-L2 = <812500 812500 850000>; - opp-microvolt-L3 = <800000 800000 850000>; - opp-microvolt-L4 = <787500 787500 850000>; - }; - opp-950000000 { - opp-hz = /bits/ 64 <950000000>; - opp-microvolt = <850000 850000 850000>; - opp-microvolt-L2 = <837500 837500 850000>; - opp-microvolt-L3 = <825000 825000 850000>; - opp-microvolt-L4 = <812500 812500 850000>; + opp-microvolt = <875000 875000 875000>; + opp-microvolt-L1 = <875000 875000 875000>; + opp-microvolt-L2 = <862500 862500 875000>; + opp-microvolt-L3 = <850000 850000 875000>; + opp-microvolt-L4 = <837500 837500 875000>; + opp-microvolt-L5 = <825000 825000 875000>; + opp-microvolt-L6 = <812500 812500 875000>; + opp-microvolt-L7 = <800000 800000 875000>; + opp-microvolt-L8 = <787500 787500 875000>; + opp-microvolt-L9 = <775000 775000 875000>; + opp-microvolt-L10 = <762500 762500 875000>; }; };