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drm/bridge: analogix_dp: Use video format information from register

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Force sync polarity to active low for RK3588.

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Icbc2b344d67dd1b8e288cfd5117b5065fd4b2142
This commit is contained in:
Wyon Bi
2022-05-28 02:00:34 +00:00
committed by Tao Huang
parent 7fbb159554
commit 2abd3af02c
2 changed files with 10 additions and 4 deletions
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11
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
View File

@@ -839,7 +839,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
/* For video bist, Video timing must be generated by register */ /* For video bist, Video timing must be generated by register */
analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_REGISTER);
/* Disable video mute */ /* Disable video mute */
analogix_dp_enable_video_mute(dp, 0); analogix_dp_enable_video_mute(dp, 0);
@@ -1748,8 +1748,13 @@ static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
/* Input video interlaces & hsync pol & vsync pol */ /* Input video interlaces & hsync pol & vsync pol */
video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); if (dp->plat_data->dev_type == RK3588_EDP) {
video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); video->v_sync_polarity = true;
video->h_sync_polarity = true;
} else {
video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
}
/* Input video dynamic_range & colorimetry */ /* Input video dynamic_range & colorimetry */
vic = drm_match_cea_mode(mode); vic = drm_match_cea_mode(mode);

3
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
View File

@@ -790,7 +790,8 @@ void analogix_dp_init_video(struct analogix_dp_device *dp)
reg = CHA_CRI(4) | CHA_CTRL; reg = CHA_CRI(4) | CHA_CTRL;
analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg); analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg);
reg = 0x0; reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3);
reg |= VALID_CTRL | F_VALID;
analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg);
reg = VID_HRES_TH(2) | VID_VRES_TH(0); reg = VID_HRES_TH(2) | VID_VRES_TH(0);