From 2accc53726a559712e5fa87d94ebf49d8270fbcc Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 19 Apr 2022 11:52:01 +0800 Subject: [PATCH] phy: rockchip: naneng-combphy: update to use T3 for PCIe TRIM According to HW signal test, the T3 parameter is the best setting for non-SSC mode, need to co-work with PPLL and DIV PF10. Signed-off-by: Kever Yang Change-Id: I3b701f714bd63e08bb5d47046c37bba6701c4f8a --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index aa86fcc766fd..43444909d1d8 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -762,11 +762,13 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) val = 0x4c; writel(val, priv->mmio + (0x1b << 2)); - /* Set up su_trim: */ - val = 0xf0; + /* Set up su_trim: T3 */ + val = 0xb0; writel(val, priv->mmio + (0xa << 2)); - val = 0x4; + val = 0x47; writel(val, priv->mmio + (0xb << 2)); + val = 0x57; + writel(val, priv->mmio + (0xd << 2)); } else if (priv->mode == PHY_TYPE_SATA) { /* downward spread spectrum +500ppm */ val = readl(priv->mmio + (0x1f << 2));