shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-10 04:48:04 +09:00
Code Issues Packages Projects Releases Wiki Activity

vpp: optimize rgb screen convert coef [1/1]

Browse Source 
PD#TV-7280

Problem:
rgb screen pattern white balance data is a little high

Solution:
optimize convert coef

Verify:
verify on TL1

Change-Id: Iae1e8134d1a48fe0bbf206dd9b148c264951da2a
Signed-off-by: MingLiang Dong <mingliang.dong@amlogic.com>
This commit is contained in:
MingLiang Dong
2019-06-28 21:03:34 +08:00
committed by Tao Zeng
parent 23ca747a1a
commit 2adfd7ee62
4 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts
View File

@@ -508,7 +508,7 @@
gamma_en = <1>;/*1:enabel ;0:disable*/
wb_en = <1>;/*1:enabel ;0:disable*/
cm_en = <1>;/*1:enabel ;0:disable*/
wb_sel = <1>;/*1:mtx ;0:gainoff*/
wb_sel = <0>;/*1:mtx ;0:gainoff*/
vlock_en = <1>;/*1:enable;0:disable*/
vlock_mode = <0x4>;
/* vlock work mode:

2
arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
View File

@@ -524,7 +524,7 @@
gamma_en = <1>;/*1:enabel ;0:disable*/
wb_en = <1>;/*1:enabel ;0:disable*/
cm_en = <1>;/*1:enabel ;0:disable*/
wb_sel = <1>;/*1:mtx ;0:gainoff*/
wb_sel = <0>;/*1:mtx ;0:gainoff*/
vlock_en = <1>;/*1:enable;0:disable*/
vlock_mode = <0x4>;
/* vlock work mode:

2
arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
View File

@@ -518,7 +518,7 @@
gamma_en = <1>;/*1:enabel ;0:disable*/
wb_en = <1>;/*1:enabel ;0:disable*/
cm_en = <1>;/*1:enabel ;0:disable*/
wb_sel = <1>;/*1:mtx ;0:gainoff*/
wb_sel = <0>;/*1:mtx ;0:gainoff*/
vlock_en = <1>;/*1:enable;0:disable*/
vlock_mode = <0x4>;
/* vlock work mode:

2
drivers/amlogic/media/video_sink/video.c
View File

@@ -10955,7 +10955,7 @@ static u32 rgb2yuv(u32 rgb)
int y, u, v;
y = ((47*r + 157*g + 16*b + 128) >> 8) + 16;
u = ((-26*r - 87*g + 112*b + 128) >> 8) + 128;
u = ((-26*r - 87*g + 113*b + 128) >> 8) + 128;
v = ((112*r - 102*g - 10*b + 128) >> 8) + 128;
return (y << 16) | (u << 8) | v;