From 2aed1b5b93d4c50789629e2fbad3f5ebf32d5868 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 28 Sep 2020 19:48:50 +0800 Subject: [PATCH] clk: rockchip: rv1126: mux clocks to none-cpll/hpll There is a lower power dissipation requirement for some products, like battery ipc, bell, etc... We have to gate cpll/hpll to reduce power dissipation. Signed-off-by: Elaine Zhang Signed-off-by: Ziyuan Xu Change-Id: I48fae621c980b6f7f7d8e8ca71171febd6c6a9a8 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-pll.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index d653403311a4..dba0503eee14 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -1252,8 +1252,12 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, /* now create the actual pll */ init.name = pll_name; +#ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE /* keep all plls untouched for now */ init.flags = flags | CLK_IGNORE_UNUSED; +#else + init.flags = flags; +#endif init.parent_names = &parent_names[0]; init.num_parents = 1;