From 2b31b121d9443e73ee4aeb99f0ce569110f8c09b Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Wed, 10 Apr 2024 20:02:24 +0800 Subject: [PATCH] drm/rockchip: drv: add mode crtc_* timing covert The mode contains two copies of timings, first are the plain and origin timings, this should keep unchanged, the second are copy from the first timing by add some computed and special fixup, this is associate with hardware. Signed-off-by: Sandy Huang Change-Id: Ib841af1bbdc970d205d8aec3f83c6238a13bdede --- drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 25 +++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c index d2273552b017..6f7bd9e2d933 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c @@ -176,11 +176,22 @@ void drm_mode_convert_to_split_mode(struct drm_display_mode *mode) hbp = mode->htotal - mode->hsync_end; mode->clock *= 2; - mode->crtc_clock *= 2; mode->hdisplay = hactive * 2; mode->hsync_start = mode->hdisplay + hfp * 2; mode->hsync_end = mode->hsync_start + hsync * 2; mode->htotal = mode->hsync_end + hbp * 2; + + hactive = mode->crtc_hdisplay; + hfp = mode->crtc_hsync_start - mode->crtc_hdisplay; + hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; + hbp = mode->crtc_htotal - mode->crtc_hsync_end; + + mode->crtc_clock *= 2; + mode->crtc_hdisplay = hactive * 2; + mode->crtc_hsync_start = mode->crtc_hdisplay + hfp * 2; + mode->crtc_hsync_end = mode->crtc_hsync_start + hsync * 2; + mode->crtc_htotal = mode->crtc_hsync_end + hbp * 2; + drm_mode_set_name(mode); } EXPORT_SYMBOL(drm_mode_convert_to_split_mode); @@ -195,11 +206,21 @@ void drm_mode_convert_to_origin_mode(struct drm_display_mode *mode) hbp = mode->htotal - mode->hsync_end; mode->clock /= 2; - mode->crtc_clock /= 2; mode->hdisplay = hactive / 2; mode->hsync_start = mode->hdisplay + hfp / 2; mode->hsync_end = mode->hsync_start + hsync / 2; mode->htotal = mode->hsync_end + hbp / 2; + + hactive = mode->crtc_hdisplay; + hfp = mode->crtc_hsync_start - mode->crtc_hdisplay; + hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; + hbp = mode->crtc_htotal - mode->crtc_hsync_end; + + mode->crtc_clock /= 2; + mode->crtc_hdisplay = hactive / 2; + mode->crtc_hsync_start = mode->crtc_hdisplay + hfp / 2; + mode->crtc_hsync_end = mode->crtc_hsync_start + hsync / 2; + mode->crtc_htotal = mode->crtc_hsync_end + hbp / 2; } EXPORT_SYMBOL(drm_mode_convert_to_origin_mode);