From 2b6899e2d0f9ce76356f69fdb7e6ac14f4e3666e Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Thu, 12 Sep 2024 15:00:01 +0800 Subject: [PATCH] ASoC: rockchip: sai: Fix mclk check Before: rockchip-sai ff810000,sai: mismatch mclk: 12287999, expected 0 (+/- 5Hz) After: rockchip-sai ff810000,sai: mismatch mclk: 12287999, at least 24576000 Fixes: 1831ca1cdc0b ("ASoC: rockchip: sai: Fix mclk rate check") Signed-off-by: Sugar Zhang Change-Id: I7addcf70104515c50463a42fc9fd7fe46a9456fd --- sound/soc/rockchip/rockchip_sai.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/sound/soc/rockchip/rockchip_sai.c b/sound/soc/rockchip/rockchip_sai.c index 69bf42feadaa..d8eb5a5c6900 100644 --- a/sound/soc/rockchip/rockchip_sai.c +++ b/sound/soc/rockchip/rockchip_sai.c @@ -620,7 +620,14 @@ static int rockchip_sai_hw_params(struct snd_pcm_substream *substream, bclk_rate = sai->fw_ratio * slot_width * ch_per_lane * params_rate(params); if (sai->is_clk_auto) clk_set_rate(sai->mclk, bclk_rate); + mclk_rate = clk_get_rate(sai->mclk); + if (mclk_rate < bclk_rate) { + dev_err(sai->dev, "Mismatch mclk: %u, at least %u\n", + mclk_rate, bclk_rate); + return -EINVAL; + } + div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate); mclk_req_rate = bclk_rate * div_bclk;