shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-09 12:17:12 +09:00
Code Issues Packages Projects Releases Wiki Activity

clk: renesas: cpg-mssr: Add missing 1ms delay into reset toggle callback

Browse Source 
[ Upstream commit 62abfd7bedc2b3d86d4209a4146f9d2b5ae21fab ]

R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page
583 Figure 9.3.1(a) Software Reset flow (A) as well as flow (B) / (C)
indicate after reset has been asserted by writing a matching reset bit
into register SRCR, it is mandatory to wait 1ms.

This 1ms delay is documented on R-Car V4H and V4M, it is currently
unclear whether S4 is affected as well.  This patch does apply the extra
delay on R-Car S4 as well.

Fix the reset driver to respect the additional delay when toggling
resets.  Drivers which use separate reset_control_(de)assert() must
assure matching delay in their driver code.

Fixes: 0ab55cf183 ("clk: renesas: cpg-mssr: Add support for R-Car V4H")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250918030552.331389-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Marek Vasut
2025-09-18 05:04:43 +02:00
committed by Greg Kroah-Hartman
parent 094b1827d2
commit 2ba9e39f1a
1 changed files with 9 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/clk/renesas/renesas-cpg-mssr.c
View File

@@ -612,8 +612,15 @@ static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
/* Reset module */
writel(bitmask, priv->base + priv->reset_regs[reg]);
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
udelay(35);
/*
* On R-Car Gen4, delay after SRCR has been written is 1ms.
* On older SoCs, delay after SRCR has been written is 35us
* (one cycle of the RCLK clock @ ca. 32 kHz).
*/
if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4)
usleep_range(1000, 2000);
else
usleep_range(35, 1000);
/* Release module from reset state */
writel(bitmask, priv->base + priv->reset_clear_regs[reg]);