From 2c48d055bc68e9abbad37fb3d284c7708d5441af Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 14 Feb 2025 08:38:39 +0800 Subject: [PATCH] mmc: dw_mmc-rockchip: Add memory clock auto-gating support Per design recommendation, memory clock could be gate if no transfer is on-flight which could help save power. This feature is introduced along with internal phase support. This patch enables the feature. Signed-off-by: Shawn Lin Change-Id: I36b90a17742da63f229e61167277bbbdc676695b --- drivers/mmc/host/dw_mmc-rockchip.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c index 2e0bd74f4030..2111d4fb5096 100644 --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c @@ -20,6 +20,8 @@ #define USRID_INTER_PHASE 0x20230001 #define SDMMC_TIMING_CON0 0x130 #define SDMMC_TIMING_CON1 0x134 +#define SDMMC_MISC_CON 0x138 +#define MEM_CLK_AUTOGATE_ENABLE BIT(5) #define ROCKCHIP_MMC_DELAY_SEL BIT(10) #define ROCKCHIP_MMC_DEGREE_MASK 0x3 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 @@ -573,6 +575,7 @@ static int dw_mci_rockchip_init(struct dw_mci *host) if (priv->usrid == USRID_INTER_PHASE) { priv->sample_clk = NULL; priv->drv_clk = NULL; + mci_writel(host, MISC_CON, MEM_CLK_AUTOGATE_ENABLE); } host->need_xfer_timer = true;