From 3c7ecd8d14eb576b121a927b28c5b479d8afe2bd Mon Sep 17 00:00:00 2001
From: LongChang Ma <chad.ma@rock-chips.com>
Date: Tue, 5 Dec 2023 20:22:10 +0800
Subject: [PATCH 1/9] media: i2c: sc3338 adapt sleep_wakeup

Signed-off-by: LongChang Ma <chad.ma@rock-chips.com>
Change-Id: I249b7a1a272aa1244b9fdd20b041d7b997bb6a27
---
 drivers/media/i2c/sc3338.c | 63 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 61 insertions(+), 2 deletions(-)

diff --git a/drivers/media/i2c/sc3338.c b/drivers/media/i2c/sc3338.c
index 8120f409c484..95452c1a45c5 100644
--- a/drivers/media/i2c/sc3338.c
+++ b/drivers/media/i2c/sc3338.c
@@ -27,6 +27,7 @@
 #include <media/v4l2-subdev.h>
 #include <linux/pinctrl/consumer.h>
 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
+#include "cam-sleep-wakeup.h"
 
 #define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x01)
 
@@ -158,6 +159,7 @@ struct sc3338 {
 	bool			is_thunderboot;
 	bool			is_first_streamoff;
 	struct preisp_hdrae_exp_s init_hdrae_exp;
+	struct cam_sw_info *cam_sw_inf;
 };
 
 #define to_sc3338(sd) container_of(sd, struct sc3338, subdev)
@@ -722,6 +724,9 @@ static long sc3338_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
 		}
 		break;
 	case PREISP_CMD_SET_HDRAE_EXP:
+		if (sc3338->cam_sw_inf)
+			memcpy(&sc3338->cam_sw_inf->hdr_ae, (struct preisp_hdrae_exp_s *)(arg),
+				sizeof(struct preisp_hdrae_exp_s));
 		break;
 	case RKMODULE_SET_QUICK_STREAM:
 
@@ -970,6 +975,8 @@ static int __sc3338_power_on(struct sc3338 *sc3338)
 		return ret;
 	}
 
+	cam_sw_regulator_bulk_init(sc3338->cam_sw_inf, SC3338_NUM_SUPPLIES, sc3338->supplies);
+
 	if (sc3338->is_thunderboot)
 		return 0;
 
@@ -1036,6 +1043,47 @@ static void __sc3338_power_off(struct sc3338 *sc3338)
 	regulator_bulk_disable(SC3338_NUM_SUPPLIES, sc3338->supplies);
 }
 
+#if IS_REACHABLE(CONFIG_VIDEO_CAM_SLEEP_WAKEUP)
+static int sc3338_resume(struct device *dev)
+{
+	int ret;
+	struct i2c_client *client = to_i2c_client(dev);
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct sc3338 *sc3338 = to_sc3338(sd);
+
+	cam_sw_prepare_wakeup(sc3338->cam_sw_inf, dev);
+
+	usleep_range(6000, 8000);
+	cam_sw_write_array(sc3338->cam_sw_inf);
+
+	if (__v4l2_ctrl_handler_setup(&sc3338->ctrl_handler))
+		dev_err(dev, "__v4l2_ctrl_handler_setup fail!");
+
+	if (sc3338->has_init_exp && sc3338->cur_mode != NO_HDR) {	// hdr mode
+		ret = sc3338_ioctl(&sc3338->subdev, PREISP_CMD_SET_HDRAE_EXP,
+				&sc3338->cam_sw_inf->hdr_ae);
+		if (ret) {
+			dev_err(&sc3338->client->dev, "set exp fail in hdr mode\n");
+			return ret;
+		}
+	}
+	return 0;
+}
+
+static int sc3338_suspend(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct sc3338 *sc3338 = to_sc3338(sd);
+
+	cam_sw_write_array_cb_init(sc3338->cam_sw_inf, client,
+		(void *)sc3338->cur_mode->reg_list, (sensor_write_array)sc3338_write_array);
+	cam_sw_prepare_sleep(sc3338->cam_sw_inf);
+
+	return 0;
+}
+#endif
+
 static int sc3338_runtime_resume(struct device *dev)
 {
 	struct i2c_client *client = to_i2c_client(dev);
@@ -1094,8 +1142,10 @@ static int sc3338_enum_frame_interval(struct v4l2_subdev *sd,
 }
 
 static const struct dev_pm_ops sc3338_pm_ops = {
-	SET_RUNTIME_PM_OPS(sc3338_runtime_suspend,
-			   sc3338_runtime_resume, NULL)
+	SET_RUNTIME_PM_OPS(sc3338_runtime_suspend, sc3338_runtime_resume, NULL)
+#if IS_REACHABLE(CONFIG_VIDEO_CAM_SLEEP_WAKEUP)
+	SET_LATE_SYSTEM_SLEEP_PM_OPS(sc3338_suspend, sc3338_resume)
+#endif
 };
 
 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
@@ -1454,6 +1504,13 @@ static int sc3338_probe(struct i2c_client *client,
 		goto err_power_off;
 #endif
 
+	if (!sc3338->cam_sw_inf) {
+		sc3338->cam_sw_inf = cam_sw_init();
+		cam_sw_clk_init(sc3338->cam_sw_inf, sc3338->xvclk, SC3338_XVCLK_FREQ);
+		cam_sw_reset_pin_init(sc3338->cam_sw_inf, sc3338->reset_gpio, 0);
+		cam_sw_pwdn_pin_init(sc3338->cam_sw_inf, sc3338->pwdn_gpio, 1);
+	}
+
 	memset(facing, 0, sizeof(facing));
 	if (strcmp(sc3338->module_facing, "back") == 0)
 		facing[0] = 'b';
@@ -1504,6 +1561,8 @@ static int sc3338_remove(struct i2c_client *client)
 	v4l2_ctrl_handler_free(&sc3338->ctrl_handler);
 	mutex_destroy(&sc3338->mutex);
 
+	cam_sw_deinit(sc3338->cam_sw_inf);
+
 	pm_runtime_disable(&client->dev);
 	if (!pm_runtime_status_suspended(&client->dev))
 		__sc3338_power_off(sc3338);

From fd1f21d6c166fd7ce0a12cfde9c722e30a2245fb Mon Sep 17 00:00:00 2001
From: LongChang Ma <chad.ma@rock-chips.com>
Date: Tue, 17 Oct 2023 10:33:45 +0800
Subject: [PATCH 2/9] media: i2c: techpoint: add tp9951 driver

Signed-off-by: LongChang Ma <chad.ma@rock-chips.com>
Change-Id: Ieee236964b12d2dc54c622641463e3bbd90c2ca6
---
 drivers/media/i2c/techpoint/Makefile          |   2 +-
 .../media/i2c/techpoint/techpoint_common.h    |   1 +
 drivers/media/i2c/techpoint/techpoint_dev.c   |  30 +-
 .../media/i2c/techpoint/techpoint_tp9951.c    | 638 ++++++++++++++++++
 .../media/i2c/techpoint/techpoint_tp9951.h    |  76 +++
 drivers/media/i2c/techpoint/techpoint_v4l2.c  |   2 +-
 6 files changed, 741 insertions(+), 8 deletions(-)
 create mode 100644 drivers/media/i2c/techpoint/techpoint_tp9951.c
 create mode 100644 drivers/media/i2c/techpoint/techpoint_tp9951.h

diff --git a/drivers/media/i2c/techpoint/Makefile b/drivers/media/i2c/techpoint/Makefile
index f7dc0e8111f7..68a820176736 100644
--- a/drivers/media/i2c/techpoint/Makefile
+++ b/drivers/media/i2c/techpoint/Makefile
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
 techpoint-objs	+= techpoint_v4l2.o techpoint_dev.o \
 		   techpoint_tp9930.o techpoint_tp2855.o \
-		   techpoint_tp9950.o
+		   techpoint_tp9950.o techpoint_tp9951.o
 obj-$(CONFIG_VIDEO_TECHPOINT)	+= techpoint.o
diff --git a/drivers/media/i2c/techpoint/techpoint_common.h b/drivers/media/i2c/techpoint/techpoint_common.h
index db556c00b8d7..c7310f3e4cda 100644
--- a/drivers/media/i2c/techpoint/techpoint_common.h
+++ b/drivers/media/i2c/techpoint/techpoint_common.h
@@ -52,6 +52,7 @@ enum techpoint_chips {
 	CHIP_TP2815,
 	CHIP_TP9930,
 	CHIP_TP9950,
+	CHIP_TP9951,
 };
 
 enum techpoint_input_type {
diff --git a/drivers/media/i2c/techpoint/techpoint_dev.c b/drivers/media/i2c/techpoint/techpoint_dev.c
index 33115f0d7b95..5692fbc34daa 100644
--- a/drivers/media/i2c/techpoint/techpoint_dev.c
+++ b/drivers/media/i2c/techpoint/techpoint_dev.c
@@ -12,6 +12,7 @@
 #include "techpoint_tp9950.h"
 #include "techpoint_tp2855.h"
 #include "techpoint_tp2815.h"
+#include "techpoint_tp9951.h"
 
 static DEFINE_MUTEX(reg_sem);
 
@@ -99,33 +100,40 @@ static int check_chip_id(struct techpoint *techpoint)
 	techpoint_read_reg(client, CHIP_ID_L_REG, &chip_id_l);
 	dev_err(dev, "chip_id_h:0x%2x chip_id_l:0x%2x\n", chip_id_h, chip_id_l);
 	if (chip_id_h == TP9930_CHIP_ID_H_VALUE &&
-	    chip_id_l == TP9930_CHIP_ID_L_VALUE) {
+	    chip_id_l == TP9930_CHIP_ID_L_VALUE) {		//tp2832
 		dev_info(&client->dev,
 			 "techpoint check chip id CHIP_TP9930 !\n");
 		techpoint->chip_id = CHIP_TP9930;
 		techpoint->input_type = TECHPOINT_DVP_BT1120;
 		return 0;
 	} else if (chip_id_h == TP2855_CHIP_ID_H_VALUE &&
-		   chip_id_l == TP2855_CHIP_ID_L_VALUE) {
+		   chip_id_l == TP2855_CHIP_ID_L_VALUE) {	//tp2855
 		dev_info(&client->dev,
 			 "techpoint check chip id CHIP_TP2855 !\n");
 		techpoint->chip_id = CHIP_TP2855;
 		techpoint->input_type = TECHPOINT_MIPI;
 		return 0;
 	} else if (chip_id_h == TP2815_CHIP_ID_H_VALUE &&
-		   chip_id_l == TP2815_CHIP_ID_L_VALUE) {
+		   chip_id_l == TP2815_CHIP_ID_L_VALUE) {	//tp2815
 		dev_info(&client->dev,
 			 "techpoint check chip id CHIP_TP2815 !\n");
 		techpoint->chip_id = CHIP_TP2855;
 		techpoint->input_type = TECHPOINT_MIPI;
 		return 0;
 	} else if (chip_id_h == TP9950_CHIP_ID_H_VALUE &&
-		   chip_id_l == TP9950_CHIP_ID_L_VALUE) {
+		   chip_id_l == TP9950_CHIP_ID_L_VALUE) {	//tp2850
 		dev_info(&client->dev,
 			 "techpoint check chip id CHIP_TP9950 !\n");
 		techpoint->chip_id = CHIP_TP9950;
 		techpoint->input_type = TECHPOINT_MIPI;
 		return 0;
+	} else if (chip_id_h == TP9951_CHIP_ID_H_VALUE &&
+		   chip_id_l == TP9951_CHIP_ID_L_VALUE) {	//tp2860
+		dev_info(&client->dev,
+			 "techpoint check chip id CHIP_TP9951 !\n");
+		techpoint->chip_id = CHIP_TP9951;
+		techpoint->input_type = TECHPOINT_MIPI;
+		return 0;
 	}
 
 	dev_info(&client->dev, "techpoint check chip id failed !\n");
@@ -143,6 +151,8 @@ int techpoint_initialize_devices(struct techpoint *techpoint)
 		tp2855_initialize(techpoint);
 	else if (techpoint->chip_id == CHIP_TP9950)
 		tp9950_initialize(techpoint);
+	else if (techpoint->chip_id == CHIP_TP9951)
+		tp9951_initialize(techpoint);
 
 	return 0;
 }
@@ -185,6 +195,10 @@ static int detect_thread_function(void *data)
 					detect_status =
 					    tp2855_get_channel_input_status
 					    (techpoint, i);
+				else if (techpoint->chip_id == CHIP_TP9951)
+					detect_status =
+					    tp9951_get_channel_input_status
+					    (techpoint, i);
 
 				if (techpoint->detect_status[i] !=
 				    detect_status) {
@@ -202,8 +216,7 @@ static int detect_thread_function(void *data)
 					else if (techpoint->chip_id == CHIP_TP2855)
 						tp2855_set_decoder_mode(client, i, detect_status);
 
-					techpoint->detect_status[i] =
-					    detect_status;
+					techpoint->detect_status[i] = detect_status;
 					need_reset_wait = 5;
 				}
 			}
@@ -273,6 +286,11 @@ static __maybe_unused int auto_detect_channel_fmt(struct techpoint *techpoint)
 		tp9950_set_channel_reso(client, 0, reso);
 	}
 
+	if (techpoint->chip_id == CHIP_TP9951) {
+		reso = tp9951_get_channel_reso(client, 0);
+		tp9951_set_channel_reso(client, 0, reso);
+	}
+
 	mutex_unlock(&reg_sem);
 
 	return 0;
diff --git a/drivers/media/i2c/techpoint/techpoint_tp9951.c b/drivers/media/i2c/techpoint/techpoint_tp9951.c
new file mode 100644
index 000000000000..8ad43fa4549b
--- /dev/null
+++ b/drivers/media/i2c/techpoint/techpoint_tp9951.c
@@ -0,0 +1,638 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * techpoint lib
+ *
+ * Copyright (C) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+#include "techpoint_tp9951.h"
+#include "techpoint_dev.h"
+
+static struct techpoint_video_modes supported_modes[] = {
+#if TP9951_DEF_PAL
+	{
+	 .bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
+	 .width = 960,
+	 .height = 576,
+	 .max_fps = {
+			.numerator = 10000,
+			.denominator = 250000,
+			},
+	 .link_freq_value = TP9951_LINK_FREQ_148M,
+	 .common_reg_list = NULL,
+	 .common_reg_size = 0,
+	 .bpp = TP9951_BITS_PER_SAMPLE,
+	 .lane = TP9951_LANES,
+	 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
+	 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
+	 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
+	 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
+	},
+#endif
+#if TP9951_DEF_NTSC
+	{
+	 .bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
+	 .width = 960,
+	 .height = 480,
+	 .max_fps = {
+			.numerator = 10000,
+			.denominator = 250000,
+			},
+	 .link_freq_value = TP9951_LINK_FREQ_148M,
+	 .common_reg_list = NULL,
+	 .common_reg_size = 0,
+	 .bpp = TP9951_BITS_PER_SAMPLE,
+	 .lane = TP9951_LANES,
+	 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
+	 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
+	 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
+	 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
+	},
+#endif
+#if TP9951_DEF_1080P
+	{
+	 .bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
+	 .width = 1920,
+	 .height = 1080,
+	 .max_fps = {
+			.numerator = 10000,
+			.denominator = 250000,
+			},
+	//	.link_freq_value = TP9951_LINK_FREQ_594M,
+	 .link_freq_value = TP9951_LINK_FREQ_297M,
+	 .common_reg_list = NULL,
+	 .common_reg_size = 0,
+	 .bpp = TP9951_BITS_PER_SAMPLE,
+	 .lane = TP9951_LANES,
+	 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
+	 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
+	 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
+	 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
+	},
+#endif
+#if TP9951_DEF_720P
+	{
+	 .bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
+	 .width = 1280,
+	 .height = 720,
+	 .max_fps = {
+			.numerator = 10000,
+			.denominator = 250000,
+			},
+	 .link_freq_value = TP9951_LINK_FREQ_297M,
+	 .common_reg_list = NULL,
+	 .common_reg_size = 0,
+	 .bpp = TP9951_BITS_PER_SAMPLE,
+	 .lane = TP9951_LANES,
+	 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
+	 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
+	 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
+	 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
+	},
+#endif
+};
+
+int tp9951_initialize(struct techpoint *techpoint)
+{
+	int array_size = 0;
+	struct i2c_client *client = techpoint->client;
+	struct device *dev = &client->dev;
+
+	techpoint->video_modes_num = ARRAY_SIZE(supported_modes);
+	array_size =
+		sizeof(struct techpoint_video_modes) * techpoint->video_modes_num;
+	techpoint->video_modes = devm_kzalloc(dev, array_size, GFP_KERNEL);
+	memcpy(techpoint->video_modes, supported_modes, array_size);
+
+	techpoint->cur_video_mode = &techpoint->video_modes[0];
+
+	return 0;
+}
+
+int tp9951_get_channel_input_status(struct techpoint *techpoint, u8 ch)
+{
+	u8 val = 0;
+	struct i2c_client *client = techpoint->client;
+
+	if (ch != 0)	// tp9951 just support 1 chn
+		return 0;
+	techpoint_write_reg(client, PAGE_REG, ch);
+	techpoint_read_reg(client, INPUT_STATUS_REG, &val);
+	dev_dbg(&client->dev, "input_status ch %d : %x\n", ch, val);
+
+	return (val & INPUT_STATUS_MASK) ? 0 : 1;
+}
+
+int tp9951_get_all_input_status(struct techpoint *techpoint, u8 *detect_status)
+{
+	u8 val = 0;
+	struct i2c_client *client = techpoint->client;
+
+	// tp9951 just support 1 chn
+	techpoint_write_reg(client, PAGE_REG, 0);
+	techpoint_read_reg(client, INPUT_STATUS_REG, &val);
+	detect_status[0] = tp9951_get_channel_input_status(techpoint, 0);
+	return 0;
+}
+
+static void tp9951_set_mipi_out(struct i2c_client *client,
+								enum techpoint_support_reso reso,
+								unsigned char lane)
+{
+	u8 tmp;
+	//mipi setting
+	techpoint_write_reg(client, 0x40, 0x08); //select MIPI page
+	techpoint_write_reg(client, 0x02, 0x7d);
+	techpoint_write_reg(client, 0x03, 0x75);
+	techpoint_write_reg(client, 0x04, 0x75);
+	techpoint_write_reg(client, 0x13, 0xef);
+	techpoint_write_reg(client, 0x20, 0x00);
+	techpoint_write_reg(client, 0x23, 0x9e);
+
+	if (lane == MIPI_1LANE) {
+		techpoint_write_reg(client, 0x21, 0x11);
+
+		if (TECHPOINT_S_RESO_1080P_30 == reso || TECHPOINT_S_RESO_1080P_25 == reso) {
+			techpoint_write_reg(client, 0x12, 0x54);
+			techpoint_write_reg(client, 0x14, 0x00);
+			techpoint_write_reg(client, 0x15, 0x02);
+
+			techpoint_write_reg(client, 0x2a, 0x08);
+			techpoint_write_reg(client, 0x2b, 0x06);
+			techpoint_write_reg(client, 0x2c, 0x12);
+			techpoint_write_reg(client, 0x2e, 0x0a);
+		} else if (TECHPOINT_S_RESO_720P_30 == reso || TECHPOINT_S_RESO_720P_25 == reso) {
+			techpoint_write_reg(client, 0x12, 0x54);
+			techpoint_write_reg(client, 0x14, 0x00);
+			techpoint_write_reg(client, 0x15, 0x12);
+
+			techpoint_write_reg(client, 0x2a, 0x04);
+			techpoint_write_reg(client, 0x2b, 0x03);
+			techpoint_write_reg(client, 0x2c, 0x0a);
+			techpoint_write_reg(client, 0x2e, 0x02);
+		} else if (TECHPOINT_S_RESO_NTSC == reso || TECHPOINT_S_RESO_PAL == reso) {
+			techpoint_write_reg(client, 0x12, 0x54);
+			techpoint_write_reg(client, 0x14, 0x51);
+			techpoint_write_reg(client, 0x15, 0x07);
+
+			techpoint_write_reg(client, 0x2a, 0x02);
+			techpoint_write_reg(client, 0x2b, 0x01);
+			techpoint_write_reg(client, 0x2c, 0x06);
+			techpoint_write_reg(client, 0x2e, 0x02);
+		}
+	} else {	// 2 lane
+		techpoint_write_reg(client, 0x21, 0x12);
+
+		if (TECHPOINT_S_RESO_1080P_30 == reso || TECHPOINT_S_RESO_1080P_25 == reso) {
+			techpoint_write_reg(client, 0x12, 0x54);
+			techpoint_write_reg(client, 0x14, 0x41);
+			techpoint_write_reg(client, 0x15, 0x02);
+
+			techpoint_write_reg(client, 0x2a, 0x04);
+			techpoint_write_reg(client, 0x2b, 0x03);
+			techpoint_write_reg(client, 0x2c, 0x0a);
+			techpoint_write_reg(client, 0x2e, 0x02);
+		} else if (TECHPOINT_S_RESO_720P_30 == reso || TECHPOINT_S_RESO_720P_25 == reso) {
+			techpoint_write_reg(client, 0x12, 0x54);
+			techpoint_write_reg(client, 0x14, 0x41);
+			techpoint_write_reg(client, 0x15, 0x12);
+
+			techpoint_write_reg(client, 0x2a, 0x02);
+			techpoint_write_reg(client, 0x2b, 0x01);
+			techpoint_write_reg(client, 0x2c, 0x06);
+			techpoint_write_reg(client, 0x2e, 0x02);
+		} else if (TECHPOINT_S_RESO_NTSC == reso || TECHPOINT_S_RESO_PAL == reso) {
+			techpoint_write_reg(client, 0x12, 0x54);
+			techpoint_write_reg(client, 0x14, 0x62);
+			techpoint_write_reg(client, 0x15, 0x07);
+
+			techpoint_write_reg(client, 0x2a, 0x02);
+			techpoint_write_reg(client, 0x2b, 0x00);
+			techpoint_write_reg(client, 0x2c, 0x04);
+			techpoint_write_reg(client, 0x2e, 0x02);
+		}
+	}
+
+	techpoint_write_reg(client, 0x40, 0x00); //back to decoder page
+	techpoint_read_reg(client, 0x06, &tmp); //PLL reset
+	techpoint_write_reg(client, 0x06, 0x80 | tmp);
+
+	techpoint_write_reg(client, 0x40, 0x08); //back to mipi page
+
+	techpoint_read_reg(client, 0x14, &tmp); //PLL reset
+	techpoint_write_reg(client, 0x14, 0x80 | tmp);
+	techpoint_write_reg(client, 0x14, tmp);
+
+	/* Enable MIPI CSI2 output */
+	techpoint_write_reg(client, 0x28, 0x02);	 //stream off
+	techpoint_write_reg(client, 0x28, 0x00);	 //stream on
+	techpoint_write_reg(client, 0x40, 0x00);	 //back to decoder page
+}
+
+int tp9951_set_channel_reso(struct i2c_client *client, int ch,
+				enum techpoint_support_reso reso)
+{
+	int val = reso;
+
+	dev_info(&client->dev, "##$$ %s", __func__);
+	techpoint_write_reg(client, 0x40, 0x00);	 //select decoder page
+	techpoint_write_reg(client, 0x06, 0x12);	 //default value
+	techpoint_write_reg(client, 0x42, 0x00);	 //common setting for all format
+	techpoint_write_reg(client, 0x4e, 0x00);	 //common setting for MIPI output
+	techpoint_write_reg(client, 0x54, 0x00);	 //common setting for MIPI output
+	techpoint_write_reg(client, 0x41, ch);		 //video MUX select
+
+	switch (val) {
+	case TECHPOINT_S_RESO_720P_25:
+#if TP9951_DEF_720P
+	default:
+#endif
+		dev_err(&client->dev, "set channel 720P_25\n");
+		techpoint_write_reg(client, 0x02, 0x42);
+		techpoint_write_reg(client, 0x07, 0xc0);
+		techpoint_write_reg(client, 0x0b, 0xc0);
+		techpoint_write_reg(client, 0x0c, 0x13);
+		techpoint_write_reg(client, 0x0d, 0x50);
+
+		techpoint_write_reg(client, 0x15, 0x13);
+		techpoint_write_reg(client, 0x16, 0x15);
+		techpoint_write_reg(client, 0x17, 0x00);
+		techpoint_write_reg(client, 0x18, 0x19);
+		techpoint_write_reg(client, 0x19, 0xd0);
+		techpoint_write_reg(client, 0x1a, 0x25);
+		techpoint_write_reg(client, 0x1c, 0x07);//1280*720, 25fps
+		techpoint_write_reg(client, 0x1d, 0xbc);//1280*720, 25fps
+
+		techpoint_write_reg(client, 0x20, 0x30);
+		techpoint_write_reg(client, 0x21, 0x84);
+		techpoint_write_reg(client, 0x22, 0x36);
+		techpoint_write_reg(client, 0x23, 0x3c);
+
+		techpoint_write_reg(client, 0x2b, 0x60);
+		techpoint_write_reg(client, 0x2c, 0x2a);
+		techpoint_write_reg(client, 0x2d, 0x30);
+		techpoint_write_reg(client, 0x2e, 0x70);
+
+		techpoint_write_reg(client, 0x30, 0x48);
+		techpoint_write_reg(client, 0x31, 0xbb);
+		techpoint_write_reg(client, 0x32, 0x2e);
+		techpoint_write_reg(client, 0x33, 0x90);
+		techpoint_write_reg(client, 0x35, 0x25);
+		techpoint_write_reg(client, 0x38, 0x00);
+		techpoint_write_reg(client, 0x39, 0x18);
+		if (STD_HDA) {
+			techpoint_write_reg(client, 0x02, 0x46);
+			techpoint_write_reg(client, 0x0d, 0x71);
+			techpoint_write_reg(client, 0x18, 0x1b);
+			techpoint_write_reg(client, 0x20, 0x40);
+			techpoint_write_reg(client, 0x21, 0x46);
+			techpoint_write_reg(client, 0x25, 0xfe);
+			techpoint_write_reg(client, 0x26, 0x01);
+			techpoint_write_reg(client, 0x2c, 0x3a);
+			techpoint_write_reg(client, 0x2d, 0x5a);
+			techpoint_write_reg(client, 0x2e, 0x40);
+			techpoint_write_reg(client, 0x30, 0x9e);
+			techpoint_write_reg(client, 0x31, 0x20);
+			techpoint_write_reg(client, 0x32, 0x10);
+			techpoint_write_reg(client, 0x33, 0x90);
+		}
+
+		tp9951_set_mipi_out(client, reso, MIPI_2LANE);	// 2 lane
+
+		break;
+	case TECHPOINT_S_RESO_1080P_25:		// FHD25
+#if TP9951_DEF_1080P
+	default:
+#endif
+		dev_err(&client->dev, "set channel 1080P_25\n");
+		techpoint_write_reg(client, 0x02, 0x40);
+		techpoint_write_reg(client, 0x07, 0xc0);
+		techpoint_write_reg(client, 0x0b, 0xc0);
+		techpoint_write_reg(client, 0x0c, 0x03);
+		techpoint_write_reg(client, 0x0d, 0x50);
+
+		techpoint_write_reg(client, 0x15, 0x03);
+		techpoint_write_reg(client, 0x16, 0xd2);
+		techpoint_write_reg(client, 0x17, 0x80);
+		techpoint_write_reg(client, 0x18, 0x29);
+		techpoint_write_reg(client, 0x19, 0x38);
+		techpoint_write_reg(client, 0x1a, 0x47);
+		techpoint_write_reg(client, 0x1c, 0x0a);//1920*1080, 25fps
+		techpoint_write_reg(client, 0x1d, 0x50);//
+
+		techpoint_write_reg(client, 0x20, 0x30);
+		techpoint_write_reg(client, 0x21, 0x84);
+		techpoint_write_reg(client, 0x22, 0x36);
+		techpoint_write_reg(client, 0x23, 0x3c);
+
+		techpoint_write_reg(client, 0x2b, 0x60);
+		techpoint_write_reg(client, 0x2c, 0x2a);
+		techpoint_write_reg(client, 0x2d, 0x30);
+		techpoint_write_reg(client, 0x2e, 0x70);
+
+		techpoint_write_reg(client, 0x30, 0x48);
+		techpoint_write_reg(client, 0x31, 0xbb);
+		techpoint_write_reg(client, 0x32, 0x2e);
+		techpoint_write_reg(client, 0x33, 0x90);
+		techpoint_write_reg(client, 0x35, 0x05);
+		techpoint_write_reg(client, 0x38, 0x00);
+		techpoint_write_reg(client, 0x39, 0x1C);
+		if (STD_HDA) {
+			techpoint_write_reg(client, 0x02, 0x44);
+			techpoint_write_reg(client, 0x0d, 0x73);
+			techpoint_write_reg(client, 0x15, 0x01);
+			techpoint_write_reg(client, 0x16, 0xf0);
+			techpoint_write_reg(client, 0x18, 0x2a);
+			techpoint_write_reg(client, 0x20, 0x3c);
+			techpoint_write_reg(client, 0x21, 0x46);
+			techpoint_write_reg(client, 0x25, 0xfe);
+			techpoint_write_reg(client, 0x26, 0x0d);
+			techpoint_write_reg(client, 0x2c, 0x3a);
+			techpoint_write_reg(client, 0x2d, 0x54);
+			techpoint_write_reg(client, 0x2e, 0x40);
+			techpoint_write_reg(client, 0x30, 0xa5);
+			techpoint_write_reg(client, 0x31, 0x86);
+			techpoint_write_reg(client, 0x32, 0xfb);
+			techpoint_write_reg(client, 0x33, 0x60);
+		}
+
+		tp9951_set_mipi_out(client, reso, MIPI_2LANE);	// 2 lane
+
+		break;
+	case TECHPOINT_S_RESO_1080P_30:		// FHD30
+		dev_err(&client->dev, "set channel PAL\n");
+			techpoint_write_reg(client, 0x02, 0x40);
+			techpoint_write_reg(client, 0x07, 0xc0);
+			techpoint_write_reg(client, 0x0b, 0xc0);
+			techpoint_write_reg(client, 0x0c, 0x03);
+			techpoint_write_reg(client, 0x0d, 0x50);
+
+			techpoint_write_reg(client, 0x15, 0x03);
+			techpoint_write_reg(client, 0x16, 0xd2);
+			techpoint_write_reg(client, 0x17, 0x80);
+			techpoint_write_reg(client, 0x18, 0x29);
+			techpoint_write_reg(client, 0x19, 0x38);
+			techpoint_write_reg(client, 0x1a, 0x47);
+			techpoint_write_reg(client, 0x1c, 0x08);  //1920*1080, 30fps
+			techpoint_write_reg(client, 0x1d, 0x98);  //
+
+			techpoint_write_reg(client, 0x20, 0x30);
+			techpoint_write_reg(client, 0x21, 0x84);
+			techpoint_write_reg(client, 0x22, 0x36);
+			techpoint_write_reg(client, 0x23, 0x3c);
+
+			techpoint_write_reg(client, 0x2b, 0x60);
+			techpoint_write_reg(client, 0x2c, 0x2a);
+			techpoint_write_reg(client, 0x2d, 0x30);
+			techpoint_write_reg(client, 0x2e, 0x70);
+
+			techpoint_write_reg(client, 0x30, 0x48);
+			techpoint_write_reg(client, 0x31, 0xbb);
+			techpoint_write_reg(client, 0x32, 0x2e);
+			techpoint_write_reg(client, 0x33, 0x90);
+
+			techpoint_write_reg(client, 0x35, 0x05);
+			techpoint_write_reg(client, 0x38, 0x00);
+			techpoint_write_reg(client, 0x39, 0x1C);
+
+			if (STD_HDA) { //AHD1080p30 extra
+				techpoint_write_reg(client, 0x02, 0x44);
+				techpoint_write_reg(client, 0x0d, 0x72);
+
+				techpoint_write_reg(client, 0x15, 0x01);
+				techpoint_write_reg(client, 0x16, 0xf0);
+				techpoint_write_reg(client, 0x18, 0x2a);
+
+				techpoint_write_reg(client, 0x20, 0x38);
+				techpoint_write_reg(client, 0x21, 0x46);
+
+				techpoint_write_reg(client, 0x25, 0xfe);
+				techpoint_write_reg(client, 0x26, 0x0d);
+
+				techpoint_write_reg(client, 0x2c, 0x3a);
+				techpoint_write_reg(client, 0x2d, 0x54);
+				techpoint_write_reg(client, 0x2e, 0x40);
+
+				techpoint_write_reg(client, 0x30, 0xa5);
+				techpoint_write_reg(client, 0x31, 0x95);
+				techpoint_write_reg(client, 0x32, 0xe0);
+				techpoint_write_reg(client, 0x33, 0x60);
+			}
+
+			tp9951_set_mipi_out(client, reso, MIPI_2LANE);	// 2 lane
+	break;
+
+	case TECHPOINT_S_RESO_PAL:
+#if TP9951_DEF_PAL
+	default:
+#endif
+
+#if CVBS_960H
+		dev_err(&client->dev, "set channel CVBS_960H\n");
+
+		techpoint_write_reg(client, 0x02, 0x47);
+		techpoint_write_reg(client, 0x0c, 0x13);
+		techpoint_write_reg(client, 0x0d, 0x51);
+
+		techpoint_write_reg(client, 0x15, 0x13);
+		techpoint_write_reg(client, 0x16, 0x76);
+		techpoint_write_reg(client, 0x17, 0x80);
+		techpoint_write_reg(client, 0x18, 0x17);
+		techpoint_write_reg(client, 0x19, 0x20);
+		techpoint_write_reg(client, 0x1a, 0x17);
+		techpoint_write_reg(client, 0x1c, 0x09);
+		techpoint_write_reg(client, 0x1d, 0x48);
+
+		techpoint_write_reg(client, 0x20, 0x48);
+		techpoint_write_reg(client, 0x21, 0x84);
+		techpoint_write_reg(client, 0x22, 0x37);
+		techpoint_write_reg(client, 0x23, 0x3f);
+
+		techpoint_write_reg(client, 0x2b, 0x70);
+		techpoint_write_reg(client, 0x2c, 0x2a);
+		techpoint_write_reg(client, 0x2d, 0x64);
+		techpoint_write_reg(client, 0x2e, 0x56);
+
+		techpoint_write_reg(client, 0x30, 0x7a);
+		techpoint_write_reg(client, 0x31, 0x4a);
+		techpoint_write_reg(client, 0x32, 0x4d);
+		techpoint_write_reg(client, 0x33, 0xf0);
+
+		techpoint_write_reg(client, 0x35, 0x65);
+		techpoint_write_reg(client, 0x38, 0x00);
+		techpoint_write_reg(client, 0x39, 0x04);
+
+#else	 //PAL 720H
+		dev_err(&client->dev, "set channel PAL 720H\n");
+		techpoint_write_reg(client, 0x02, 0x47);
+		techpoint_write_reg(client, 0x06, 0x32);
+		techpoint_write_reg(client, 0x0c, 0x13);
+		techpoint_write_reg(client, 0x0d, 0x51);
+
+		techpoint_write_reg(client, 0x15, 0x03);
+		techpoint_write_reg(client, 0x16, 0xf0);
+		techpoint_write_reg(client, 0x17, 0xa0);
+		techpoint_write_reg(client, 0x18, 0x17);
+		techpoint_write_reg(client, 0x19, 0x20);
+		techpoint_write_reg(client, 0x1a, 0x15);
+		techpoint_write_reg(client, 0x1c, 0x06);
+		techpoint_write_reg(client, 0x1d, 0xc0);
+
+		techpoint_write_reg(client, 0x20, 0x48);
+		techpoint_write_reg(client, 0x21, 0x84);
+		techpoint_write_reg(client, 0x22, 0x37);
+		techpoint_write_reg(client, 0x23, 0x3f);
+
+		techpoint_write_reg(client, 0x2b, 0x70);
+		techpoint_write_reg(client, 0x2c, 0x2a);
+		techpoint_write_reg(client, 0x2d, 0x4b);
+		techpoint_write_reg(client, 0x2e, 0x56);
+
+		techpoint_write_reg(client, 0x30, 0x7a);
+		techpoint_write_reg(client, 0x31, 0x4a);
+		techpoint_write_reg(client, 0x32, 0x4d);
+		techpoint_write_reg(client, 0x33, 0xfb);
+
+		techpoint_write_reg(client, 0x35, 0x65);
+		techpoint_write_reg(client, 0x38, 0x00);
+		techpoint_write_reg(client, 0x39, 0x04);
+#endif
+		tp9951_set_mipi_out(client, reso, MIPI_2LANE);	// 2 lane
+
+		break;
+	case TECHPOINT_S_RESO_NTSC:
+#if TP9951_DEF_NTSC
+	default:
+#endif
+
+#if CVBS_960H
+		dev_err(&client->dev, "set channel NTSC CVBS_960H\n");
+		techpoint_write_reg(client, 0x02, 0x47);
+		techpoint_write_reg(client, 0x0c, 0x13);
+		techpoint_write_reg(client, 0x0d, 0x50);
+
+		techpoint_write_reg(client, 0x15, 0x13);
+		techpoint_write_reg(client, 0x16, 0x60);
+		techpoint_write_reg(client, 0x17, 0x80);
+		techpoint_write_reg(client, 0x18, 0x12);
+		techpoint_write_reg(client, 0x19, 0xf0);
+		techpoint_write_reg(client, 0x1a, 0x07);
+		techpoint_write_reg(client, 0x1c, 0x09);
+		techpoint_write_reg(client, 0x1d, 0x38);
+
+		techpoint_write_reg(client, 0x20, 0x40);
+		techpoint_write_reg(client, 0x21, 0x84);
+		techpoint_write_reg(client, 0x22, 0x36);
+		techpoint_write_reg(client, 0x23, 0x3c);
+
+		techpoint_write_reg(client, 0x2b, 0x70);
+		techpoint_write_reg(client, 0x2c, 0x2a);
+		techpoint_write_reg(client, 0x2d, 0x68);
+		techpoint_write_reg(client, 0x2e, 0x57);
+
+		techpoint_write_reg(client, 0x30, 0x62);
+		techpoint_write_reg(client, 0x31, 0xbb);
+		techpoint_write_reg(client, 0x32, 0x96);
+		techpoint_write_reg(client, 0x33, 0xc0);
+
+		techpoint_write_reg(client, 0x35, 0x65);
+		techpoint_write_reg(client, 0x38, 0x00);
+		techpoint_write_reg(client, 0x39, 0x04);
+#else
+		dev_err(&client->dev, "set channel NTSC 720H\n");
+		techpoint_write_reg(client, 0x02, 0x47);
+		techpoint_write_reg(client, 0x0c, 0x13);
+		techpoint_write_reg(client, 0x0d, 0x50);
+
+		techpoint_write_reg(client, 0x15, 0x03);
+		techpoint_write_reg(client, 0x16, 0xd6);
+		techpoint_write_reg(client, 0x17, 0xa0);
+		techpoint_write_reg(client, 0x18, 0x12);
+		techpoint_write_reg(client, 0x19, 0xf0);
+		techpoint_write_reg(client, 0x1a, 0x05);
+		techpoint_write_reg(client, 0x1c, 0x06);
+		techpoint_write_reg(client, 0x1d, 0xb4);
+
+		techpoint_write_reg(client, 0x20, 0x40);
+		techpoint_write_reg(client, 0x21, 0x84);
+		techpoint_write_reg(client, 0x22, 0x36);
+		techpoint_write_reg(client, 0x23, 0x3c);
+
+		techpoint_write_reg(client, 0x2b, 0x70);
+		techpoint_write_reg(client, 0x2c, 0x2a);
+		techpoint_write_reg(client, 0x2d, 0x4b);
+		techpoint_write_reg(client, 0x2e, 0x57);
+
+		techpoint_write_reg(client, 0x30, 0x62);
+		techpoint_write_reg(client, 0x31, 0xbb);
+		techpoint_write_reg(client, 0x32, 0x96);
+		techpoint_write_reg(client, 0x33, 0xcb);
+
+		techpoint_write_reg(client, 0x35, 0x65);
+		techpoint_write_reg(client, 0x38, 0x00);
+		techpoint_write_reg(client, 0x39, 0x04);
+#endif
+		break;
+	}
+
+#if TECHPOINT_TEST_PATTERN
+	techpoint_write_reg(client, 0x2a, 0x3c);
+#endif
+
+	return 0;
+}
+
+// detect for reference only, the accuracy may be affected by the current invoked decoding standard.
+int tp9951_get_channel_reso(struct i2c_client *client, int ch)
+{
+	u8 detect_fmt = 0xff;
+	u8 reso = 0xff;
+
+	techpoint_write_reg(client, 0x40, ch);
+	techpoint_read_reg(client, 0x03, &detect_fmt);
+	reso = detect_fmt & 0x7;
+
+	switch (reso) {
+	case TP9951_CVSTD_720P_25:
+#if TP9951_DEF_720P
+	default:
+#endif
+		dev_err(&client->dev, "detect channel %d 720P_25\n", ch);
+		return TECHPOINT_S_RESO_720P_25;
+	case TP9951_CVSTD_1080P_25:
+#if TP9951_DEF_1080P
+	default:
+#endif
+		dev_err(&client->dev, "detect channel %d 1080P_25\n", ch);
+		return TECHPOINT_S_RESO_1080P_25;
+	case TP9951_CVSTD_PAL:
+#if TP9951_DEF_PAL
+	default:
+#endif
+		dev_err(&client->dev, "detect channel %d PAL\n", ch);
+		return TECHPOINT_S_RESO_PAL;
+	case TP9951_CVSTD_NTSC:
+#if TP9951_DEF_NTSC
+	default:
+#endif
+		dev_err(&client->dev, "detect channel %d NTSC\n", ch);
+		return TECHPOINT_S_RESO_NTSC;
+	}
+
+	return reso;
+}
+
+int tp9951_set_quick_stream(struct i2c_client *client, u32 stream)
+{
+	// mutex_lock(&techpoint->mutex);
+	if (stream) {
+		techpoint_write_reg(client, 0x40, 0x8);
+		techpoint_write_reg(client, 0x28, 0x0);
+	} else {
+		techpoint_write_reg(client, 0x40, 0x8);
+		techpoint_write_reg(client, 0x28, 0x2);
+		usleep_range(40 * 1000, 50 * 1000);
+	}
+	// mutex_unlock(&techpoint->mutex);
+	return 0;
+}
diff --git a/drivers/media/i2c/techpoint/techpoint_tp9951.h b/drivers/media/i2c/techpoint/techpoint_tp9951.h
new file mode 100644
index 000000000000..76cbda2d7ef9
--- /dev/null
+++ b/drivers/media/i2c/techpoint/techpoint_tp9951.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * techpoint tp9951 regs
+ *
+ * Copyright (C) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _TECHPOINT_TP9951_H
+#define _TECHPOINT_TP9951_H
+
+#include "techpoint_common.h"
+
+#define DEBUG
+
+#define TP9951_DEF_1080P 1
+#define TP9951_DEF_720P 0
+#define TP9951_DEF_PAL 0
+#define TP9951_DEF_NTSC 0
+
+#define STD_TVI 0
+#define STD_HDA 1
+
+// device id 0x2860
+#define TP9951_CHIP_ID_H_REG	  0xFE
+#define TP9951_CHIP_ID_H_VALUE	  0x28
+#define TP9951_CHIP_ID_L_REG	  0xFF
+#define TP9951_CHIP_ID_L_VALUE	  0x60
+
+#define TP9951_LINK_FREQ_148M		(148500000UL >> 1)
+#define TP9951_LINK_FREQ_297M		(297000000UL >> 1)
+#define TP9951_LINK_FREQ_594M		(594000000UL >> 1)
+#define TP9951_LANES				2
+#define TP9951_BITS_PER_SAMPLE		8
+
+enum tp9952_support_mipi_lane {
+	MIPI_2LANE,
+	MIPI_1LANE,
+};
+
+#define CVBS_960H					(0) //1->960H 0->720H
+
+enum tp9951_support_reso {
+	TP9951_CVSTD_720P_60 = 0,
+	TP9951_CVSTD_720P_50,
+	TP9951_CVSTD_1080P_30,
+	TP9951_CVSTD_1080P_25,
+	TP9951_CVSTD_720P_30,
+	TP9951_CVSTD_720P_25,
+	TP9951_CVSTD_SD,
+	TP9951_CVSTD_OTHER,
+	TP9951_CVSTD_720P_275,
+	TP9951_CVSTD_QHD30,	//960×540 only support with 2lane mode
+	TP9951_CVSTD_QHD25,	 //960×540 only support with 2lane mode
+	TP9951_CVSTD_PAL,
+	TP9951_CVSTD_NTSC,
+	TP9951_CVSTD_UVGA25,  //1280x960p25, must use with MIPI_4CH4LANE_445M
+	TP9951_CVSTD_UVGA30,  //1280x960p30, must use with MIPI_4CH4LANE_445M
+	TP9951_CVSTD_A_UVGA30,	//HDA 1280x960p30, must use with MIPI_4CH4LANE_378M
+	TP9951_CVSTD_F_UVGA30,	//FH 1280x960p30, 1800x1000
+	TP9951_CVSTD_HD30864, //total 1600x900 86.4M
+	TP9951_CVSTD_HD30HDR, //special 720p30 with ISX019/SC120AT,total 1650x900
+	TP9951_CVSTD_1080P_60,//only support with 2lane mode
+	TP9951_CVSTD_1080P_50,//only support with 2lane mode
+	TP9951_CVSTD_1080P_28,
+	TP9951_CVSTD_1080P_275,
+};
+
+int tp9951_initialize(struct techpoint *techpoint);
+int tp9951_get_channel_input_status(struct techpoint *techpoint, u8 ch);
+int tp9951_get_all_input_status(struct techpoint *techpoint, u8 *detect_status);
+int tp9951_set_channel_reso(struct i2c_client *client, int ch,
+				enum techpoint_support_reso reso);
+int tp9951_get_channel_reso(struct i2c_client *client, int ch);
+int tp9951_set_quick_stream(struct i2c_client *client, u32 stream);
+
+#endif // _TECHPOINT_TP9951_H
diff --git a/drivers/media/i2c/techpoint/techpoint_v4l2.c b/drivers/media/i2c/techpoint/techpoint_v4l2.c
index 82ef4480323d..39f6a3b71e77 100644
--- a/drivers/media/i2c/techpoint/techpoint_v4l2.c
+++ b/drivers/media/i2c/techpoint/techpoint_v4l2.c
@@ -860,6 +860,7 @@ static const struct of_device_id techpoint_of_match[] = {
 	{ .compatible = "techpoint,tp2815" },
 	{ .compatible = "techpoint,tp9930" },
 	{ .compatible = "techpoint,tp9950" },
+	{ .compatible = "techpoint,tp9951" },
 	{ },
 };
 
@@ -1297,7 +1298,6 @@ static int techpoint_audio_probe(struct techpoint *techpoint)
 	}
 
 	if (techpoint->chip_id == CHIP_TP9930) {
-
 		techpoint_write_reg(techpoint->client, 0x40, 0x00);
 		for (i = 0; i < 0xff; i++)
 			techpoint_write_reg(techpoint->client, i, 0xbb);

From 7f2e38980d3437e830f654ed228c088483fb0a93 Mon Sep 17 00:00:00 2001
From: Cai YiWei <cyw@rock-chips.com>
Date: Wed, 6 Dec 2023 09:13:32 +0800
Subject: [PATCH 3/9] media: rockchip: isp: version v2.4.0

Change-Id: If8379fbed725c542c0473fd0c6797effd896e03a
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
---
 drivers/media/platform/rockchip/isp/version.h | 24 +++++++++++++++++++
 include/uapi/linux/rk-isp2-config.h           |  2 +-
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/media/platform/rockchip/isp/version.h b/drivers/media/platform/rockchip/isp/version.h
index c4c7254c473a..8981e4709131 100644
--- a/drivers/media/platform/rockchip/isp/version.h
+++ b/drivers/media/platform/rockchip/isp/version.h
@@ -459,6 +459,30 @@
  * 11.fix image effect for frame two-run
  * 12.fix underperformance for frame two-run
  * 13.support unite mode for isp32
+ *
+ * v2.4.0 (AIQ v5.4.0)
+ * 1.fix rv1106g3 4k cmsk right
+ * 2.fix image effect for rv1106 4k
+ * 3.add RKISP_VICAP_CMD_QUICK_STREAM CMD
+ * 4.support suspend and resume
+ * 5.pm add call sensor s_power
+ * 6.suspend resume with rtt
+ * 7.fix resume hold by lut error
+ * 8.fix rv1106g3 4k can't cmsk rightmost
+ * 9.fix rv1106 resume no output
+ * 10.support to do reset in online mode
+ * 11.support change work mode to online with quick stream
+ * 12.fix build warning
+ * 13.frame timestamp change to sof
+ * 14.fix wnd_num cause array access out of bounds
+ * 15.fix rv1106 cycle kill rkipc null pointer
+ * 16.fix power_cnt if error
+ * 17.fix rockit set_fmt stuck
+ * 18.fix info2ddr no enable
+ * 19.fix reset can't open
+ * 20.more time to wait isp end
+ * 21.add mode for rv1106 suspend without rtt
+ * 22.fix is_on false cause pm isp die
  */
 
 #define RKISP_DRIVER_VERSION RKISP_API_VERSION
diff --git a/include/uapi/linux/rk-isp2-config.h b/include/uapi/linux/rk-isp2-config.h
index 8d1db6506600..50949e0752bc 100644
--- a/include/uapi/linux/rk-isp2-config.h
+++ b/include/uapi/linux/rk-isp2-config.h
@@ -11,7 +11,7 @@
 #include <linux/types.h>
 #include <linux/v4l2-controls.h>
 
-#define RKISP_API_VERSION		KERNEL_VERSION(2, 3, 0)
+#define RKISP_API_VERSION		KERNEL_VERSION(2, 4, 0)
 
 /****************ISP SUBDEV IOCTL*****************************/
 

From 520ae493e916508c38580e330316210d62d308de Mon Sep 17 00:00:00 2001
From: Lin Jianhua <linjh@rock-chips.com>
Date: Wed, 16 Aug 2023 10:03:58 +0800
Subject: [PATCH 4/9] arm64: dts: rockchip: add PCIe EP Board for rk3568

Change-Id: Iabfd99bb6d6934255cc82cc773dc80ba822e415b
Signed-off-by: Lin Jianhua <linjh@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/Makefile         |   1 +
 .../rk3568-pcie-ep-lp4x-v10-linux.dts         | 641 ++++++++++++++++++
 2 files changed, 642 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-pcie-ep-lp4x-v10-linux.dts

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 88d2ff218476..66ef41c85240 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -168,6 +168,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux-spi-nand.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux-spi-nand.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-pcie-ep-lp4x-v10-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-sd0-android.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-sd0-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-x0-android.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pcie-ep-lp4x-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3568-pcie-ep-lp4x-v10-linux.dts
new file mode 100644
index 000000000000..4f255e1a635c
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-pcie-ep-lp4x-v10-linux.dts
@@ -0,0 +1,641 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/rk-input.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "Rockchip RK3568 PCIe EP LP4X V10 Board";
+	compatible = "rockchip,rk3568-pcie-ep-lp4x-v10", "rockchip,rk3568";
+
+	adc_keys: adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		vol-up-key {
+			label = "volume up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <1750>;
+		};
+	};
+
+	chosen: chosen {
+		bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait default_hugepagesz=32M hugepagesz=32M hugepages=1";
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	fiq-debugger {
+		compatible = "rockchip,fiq-debugger";
+		rockchip,serial-id = <2>;
+		rockchip,wake-irq = <0>;
+		/* If enable uart uses irq instead of fiq */
+		rockchip,irq-mode-enable = <1>;
+		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
+		interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart2m0_xfer>;
+		status = "okay";
+	};
+
+	hdmi_sound: hdmi-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <128>;
+		simple-audio-card,name = "rockchip,hdmi";
+		status = "disabled";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0_8ch>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&hdmi>;
+		};
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		work_led: work {
+			gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		bar0_region: bar0-region@0x3c000000 {
+			reg = <0x0 0x3c000000 0x0 0x00400000>;
+		};
+		bar2_region: bar2-region@0x40000000 {
+			reg = <0x0 0x40000000 0x0 0x04000000>;
+		};
+	};
+
+	test-power {
+		status = "okay";
+	};
+
+	vcc3v3_pcie: gpio-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <5000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_sys>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+	};
+
+	vcc5v0_otg: vcc5v0-otg-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_sys>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_otg_en>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vccio_1v8: vccio-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vccio_1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vccio_3v3: vccio-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vccio_3v3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vdd_gpu: vdd-gpu {
+		compatible = "pwm-regulator";
+		pwms = <&pwm0 0 5000 1>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <810000>;
+		regulator-max-microvolt = <1100000>;
+		regulator-init-microvolt = <920000>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-settling-time-up-us = <250>;
+		pwm-supply = <&vcc3v3_sys>;
+		status = "okay";
+	};
+
+	vdd_logic: vdd-logic {
+		compatible = "pwm-regulator";
+		pwms = <&pwm1 0 5000 1>;
+		regulator-name = "vdd_logic";
+		regulator-min-microvolt = <810000>;
+		regulator-max-microvolt = <1000000>;
+		regulator-init-microvolt = <920000>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-settling-time-up-us = <250>;
+		pwm-supply = <&vcc3v3_sys>;
+		status = "okay";
+	};
+
+	vdd_npu: vdd-npu {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 5000 1>;
+		regulator-name = "vdd_npu";
+		regulator-min-microvolt = <810000>;
+		regulator-max-microvolt = <1100000>;
+		regulator-init-microvolt = <920000>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-settling-time-up-us = <250>;
+		pwm-supply = <&vcc3v3_sys>;
+		status = "okay";
+	};
+};
+
+&bus_npu {
+	bus-supply = <&vdd_logic>;
+	pvtm-supply = <&vdd_cpu>;
+	status = "okay";
+};
+
+&can1 {
+	assigned-clocks = <&cru CLK_CAN0>;
+	assigned-clock-rates = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&can1m0_pins>;
+	status = "okay";
+};
+
+&combphy0_us {
+	status = "okay";
+};
+
+&combphy1_usq {
+	status = "okay";
+};
+
+&combphy2_psq {
+	 status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&dfi {
+	status = "okay";
+};
+
+&dmc {
+	center-supply = <&vdd_logic>;
+	status = "okay";
+};
+
+&display_subsystem {
+	status = "okay";
+};
+
+&gmac0 {
+	phy-mode = "rgmii";
+	clock_in_out = "output";
+
+	snps,reset-gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+	assigned-clock-rates = <0>, <125000000>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+
+	tx_delay = <0x3c>;
+	rx_delay = <0x2f>;
+
+	phy-handle = <&rgmii_phy0>;
+	status = "okay";
+};
+
+&gmac1 {
+	phy-mode = "rgmii";
+	clock_in_out = "output";
+
+	snps,reset-gpio = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+	assigned-clock-rates = <0>, <125000000>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_rgmii_bus>;
+
+	tx_delay = <0x4f>;
+	rx_delay = <0x26>;
+
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	status = "okay";
+	rockchip,phy-table =
+		<92812500  0x8009 0x0000 0x0270>,
+		<165000000 0x800b 0x0000 0x026d>,
+		<185625000 0x800b 0x0000 0x01ed>,
+		<297000000 0x800b 0x0000 0x01ad>,
+		<594000000 0x8029 0x0000 0x0088>,
+		<000000000 0x0000 0x0000 0x0000>;
+};
+
+&hdmi_in_vp0 {
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	vdd_cpu: rk8600@40 {
+		compatible = "rockchip,rk8600";
+		reg = <0x40>;
+		vin-supply = <&vcc3v3_sys>;
+		regulator-compatible = "rk860x-reg";
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <2300>;
+		rockchip,suspend-voltage-selector = <1>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2m1_xfer>;
+};
+
+&i2c3 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3m1_xfer>;
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&iep {
+	status = "okay";
+};
+
+&iep_mmu {
+	status = "okay";
+};
+
+&jpegd {
+	status = "okay";
+};
+
+&jpegd_mmu {
+	status = "okay";
+};
+
+&mdio0 {
+	rgmii_phy0: phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+	};
+};
+
+&mpp_srv {
+	status = "okay";
+};
+
+&pcie2x1 {
+	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pcie30phy {
+	status = "okay";
+};
+
+&pcie3x2 {
+	compatible = "rockchip,rk3568-pcie-std-ep";
+	memory-region = <&bar0_region>, <&bar2_region>;
+	memory-region-names = "bar0", "bar2";
+	status = "okay";
+};
+
+&pinctrl {
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_otg_en: vcc5v0-otg-en {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmuio2-supply = <&vccio_3v3>;
+	vccio1-supply = <&vccio_3v3>;
+	vccio3-supply = <&vccio_3v3>;
+	vccio4-supply = <&vccio_3v3>;
+	vccio5-supply = <&vccio_3v3>;
+	vccio6-supply = <&vccio_3v3>;
+	vccio7-supply = <&vccio_3v3>;
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&rk_rga {
+	status = "okay";
+};
+
+&rkvdec {
+	status = "okay";
+};
+
+&rkvdec_mmu {
+	status = "okay";
+};
+
+&rkvenc {
+	venc-supply = <&vdd_logic>;
+	status = "okay";
+};
+
+&rkvenc_mmu {
+	status = "okay";
+};
+
+&rknpu {
+	rknpu-supply = <&vdd_npu>;
+	status = "okay";
+};
+
+&rknpu_mmu {
+	status = "okay";
+};
+
+&saradc {
+	status = "okay";
+	vref-supply = <&vccio_1v8>;
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	max-frequency = <200000000>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	max-frequency = <150000000>;
+	no-sdio;
+	no-mmc;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vccio_3v3>;
+	vqmmc-supply = <&vccio_3v3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	status = "okay";
+};
+
+&sdmmc2 {
+	max-frequency = <150000000>;
+	no-sd;
+	no-mmc;
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	//mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&sfc {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <75000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&spi0 {
+	status = "okay";
+	pinctrl-names = "default", "high_speed";
+	pinctrl-0 = <&spi0m1_cs0 &spi0m1_pins>;
+	pinctrl-1 = <&spi0m1_cs0 &spi0m1_pins_hs>;
+};
+
+&spi2 {
+	status = "okay";
+	pinctrl-names = "default", "high_speed";
+	pinctrl-0 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins>;
+	pinctrl-1 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins_hs>;
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3m1_xfer>;
+};
+
+/* RS485 */
+&uart4 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart4m0_xfer &uart4m0_ctsn &uart4m0_rtsn>;
+};
+
+&uart7 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart7m1_xfer>;
+};
+
+&u2phy0_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+	vbus-supply = <&vcc5v0_otg>;
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3 {
+	dr_mode = "otg";
+	extcon = <&usb2phy0>;
+	status = "okay";
+};
+
+&usbdrd30 {
+	status = "okay";
+};
+
+&usbhost_dwc3 {
+	status = "okay";
+};
+
+&usbhost30 {
+	status = "okay";
+};
+
+&vdpu {
+	status = "okay";
+};
+
+&vdpu_mmu {
+	status = "okay";
+};
+
+&vepu {
+	status = "okay";
+};
+
+&vepu_mmu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+};
+
+&vop_mmu {
+	status = "okay";
+};

From b202c1caa3fe5b35edec9dc03397bb0beedac375 Mon Sep 17 00:00:00 2001
From: Lin Jianhua <linjh@rock-chips.com>
Date: Thu, 7 Dec 2023 10:46:24 +0800
Subject: [PATCH 5/9] arm64: configs: add rockchip_linux_pcie_ep.config for
 some case use PCIe EP Card

Change-Id: Ia78d3e26ba1153b1fb0889dccb04c238534ff325
Signed-off-by: Lin Jianhua <linjh@rock-chips.com>
---
 arch/arm64/configs/rockchip_linux_pcie_ep.config | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 arch/arm64/configs/rockchip_linux_pcie_ep.config

diff --git a/arch/arm64/configs/rockchip_linux_pcie_ep.config b/arch/arm64/configs/rockchip_linux_pcie_ep.config
new file mode 100644
index 000000000000..409075c578f8
--- /dev/null
+++ b/arch/arm64/configs/rockchip_linux_pcie_ep.config
@@ -0,0 +1,7 @@
+CONFIG_HUGETLBFS=y
+CONFIG_PCIE_DW_ROCKCHIP_EP=y
+CONFIG_PCIE_FUNC_RKEP=y
+CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
+# CONFIG_CGROUP_HUGETLB is not set
+CONFIG_HUGETLB_PAGE=y
+# CONFIG_PCIE_FUNC_RKEP_USERPAGES is not set

From 0350e3c5ed2a7e78d7c6d48863e0d3af751f8040 Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Wed, 6 Dec 2023 20:49:04 +0800
Subject: [PATCH 6/9] PCI: rockchip: dw: Fix resize bar capability for EP

Avoid RC attempting to modify EP bar strategy.

Change-Id: Icd8fefe9d6a09ad4a4845af83d6dd6b80c78d5bc
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
 drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
index 31e84f74f2c7..b20e3d9af6e5 100644
--- a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
@@ -528,18 +528,18 @@ static void rockchip_pcie_resize_bar(struct rockchip_pcie *rockchip)
 
 	/* Resize BAR0 4M 32bits, BAR2 64M 64bits-pref, BAR4 1MB 32bits */
 	bar = BAR_0;
-	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0);
+	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0x40);
 	dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0x2c0);
 	rockchip_pcie_ep_set_bar_flag(rockchip, bar, PCI_BASE_ADDRESS_MEM_TYPE_32);
 
 	bar = BAR_2;
-	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0);
+	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0x400);
 	dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0x6c0);
 	rockchip_pcie_ep_set_bar_flag(rockchip, bar,
 				      PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64);
 
 	bar = BAR_4;
-	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0);
+	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0x10);
 	dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0xc0);
 	rockchip_pcie_ep_set_bar_flag(rockchip, bar, PCI_BASE_ADDRESS_MEM_TYPE_32);
 

From a34de858578fccf80225f6674f749db57ebee6fc Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Thu, 30 Nov 2023 14:27:29 +0800
Subject: [PATCH 7/9] PCI: rockchip: dw: Remove useless apis

The PCIe dbi base is accessible in userspace by mmap, then the
elbi_data and bar0 physical address is visible from dbi base mmap
space.

Change-Id: I5abd5921d2c7fd361e098ded568a470ff1b67ad2
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
 .../pci/controller/dwc/pcie-dw-ep-rockchip.c  | 24 -------------------
 include/uapi/linux/rk-pcie-ep.h               | 10 --------
 2 files changed, 34 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
index b20e3d9af6e5..29a8f8ae11d6 100644
--- a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
@@ -970,27 +970,12 @@ static int pcie_ep_release(struct inode *inode, struct file *file)
 static long pcie_ep_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 {
 	struct rockchip_pcie *rockchip = (struct rockchip_pcie *)file->private_data;
-	struct pcie_ep_user_data msg;
 	struct pcie_ep_dma_cache_cfg cfg;
 	void __user *uarg = (void __user *)arg;
 	int i, ret;
 	enum pcie_ep_mmap_resource mmap_res;
 
 	switch (cmd) {
-	case PCIE_DMA_GET_ELBI_DATA:
-		for (i = 4; i <= 6; i++)
-			msg.elbi_app_user[i - 4] = dw_pcie_readl_dbi(&rockchip->pci,
-								     PCIE_ELBI_LOCAL_BASE + i * 4);
-		for (i = 8; i <= 15; i++)
-			msg.elbi_app_user[i - 5] = dw_pcie_readl_dbi(&rockchip->pci,
-								     PCIE_ELBI_LOCAL_BASE + i * 4);
-
-		ret = copy_to_user(uarg, &msg, sizeof(msg));
-		if (ret) {
-			dev_err(rockchip->pci.dev, "failed to get elbi data\n");
-			return -EFAULT;
-		}
-		break;
 	case PCIE_DMA_CACHE_INVALIDE:
 		ret = copy_from_user(&cfg, uarg, sizeof(cfg));
 		if (ret) {
@@ -1017,15 +1002,6 @@ static long pcie_ep_ioctl(struct file *file, unsigned int cmd, unsigned long arg
 		rockchip->obj_info->irq_type_rc = OBJ_IRQ_USER;
 		rockchip_pcie_raise_msi_irq(rockchip, PCIe_CLIENT_MSI_OBJ_IRQ);
 		break;
-	case PCIE_EP_GET_USER_INFO:
-		msg.bar0_phys_addr = rockchip->ib_target_address[0];
-
-		ret = copy_to_user(uarg, &msg, sizeof(msg));
-		if (ret) {
-			dev_err(rockchip->pci.dev, "failed to get elbi data\n");
-			return -EFAULT;
-		}
-		break;
 	case PCIE_EP_SET_MMAP_RESOURCE:
 		ret = copy_from_user(&mmap_res, uarg, sizeof(mmap_res));
 		if (ret) {
diff --git a/include/uapi/linux/rk-pcie-ep.h b/include/uapi/linux/rk-pcie-ep.h
index 345c6c2e9e86..fe1e677c1ad4 100644
--- a/include/uapi/linux/rk-pcie-ep.h
+++ b/include/uapi/linux/rk-pcie-ep.h
@@ -24,14 +24,6 @@
 /* Application status*/
 #define RKEP_SMODE_APPRDY       0x20
 
-/*
- * rockchip pcie driver elbi ioctrl output data
- */
-struct pcie_ep_user_data {
-	__u64 bar0_phys_addr;
-	__u32 elbi_app_user[11];
-};
-
 /*
  * rockchip driver cache ioctrl input param
  */
@@ -101,12 +93,10 @@ struct pcie_ep_obj_info {
 };
 
 #define PCIE_BASE	'P'
-#define PCIE_DMA_GET_ELBI_DATA		_IOR(PCIE_BASE, 0, struct pcie_ep_user_data)
 #define PCIE_DMA_CACHE_INVALIDE		_IOW(PCIE_BASE, 1, struct pcie_ep_dma_cache_cfg)
 #define PCIE_DMA_CACHE_FLUSH		_IOW(PCIE_BASE, 2, struct pcie_ep_dma_cache_cfg)
 #define PCIE_DMA_IRQ_MASK_ALL		_IOW(PCIE_BASE, 3, int)
 #define PCIE_DMA_RAISE_MSI_OBJ_IRQ_USER	_IOW(PCIE_BASE, 4, int)
-#define PCIE_EP_GET_USER_INFO		_IOR(PCIE_BASE, 5, struct pcie_ep_user_data)
 #define PCIE_EP_SET_MMAP_RESOURCE	_IOW(PCIE_BASE, 6, int)
 #define PCIE_EP_RAISE_ELBI		_IOW(PCIE_BASE, 7, int)
 #define PCIE_EP_REQUEST_VIRTUAL_ID	_IOR(PCIE_BASE, 16, int)

From bda0d3d45126f6c67df31e1db781f84bdcf1e349 Mon Sep 17 00:00:00 2001
From: William Wu <william.wu@rock-chips.com>
Date: Thu, 7 Dec 2023 11:35:57 +0800
Subject: [PATCH 8/9] ARM: dts: rockchip: rv1126: Remove unused quirk for usb

This patch remove unused property "snps,xhci-trb-ent-quirk"
for rv1126 usb controller.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ic6a713261219cb75b7739f2db8ff5dddfafe67b1
---
 arch/arm/boot/dts/rv1126.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi
index 73a17ab904ee..729345d80dac 100644
--- a/arch/arm/boot/dts/rv1126.dtsi
+++ b/arch/arm/boot/dts/rv1126.dtsi
@@ -2569,7 +2569,6 @@
 			snps,dis-del-phy-power-chg-quirk;
 			snps,tx-ipgap-linecheck-dis-quirk;
 			snps,tx-fifo-resize;
-			snps,xhci-trb-ent-quirk;
 			snps,usb2-lpm-disable;
 			snps,parkmode-disable-hs-quirk;
 			status = "disabled";

From 36e981880962e2f7580e42a9ea125a6a04c218ad Mon Sep 17 00:00:00 2001
From: Tao Huang <huangtao@rock-chips.com>
Date: Fri, 8 Dec 2023 14:28:16 +0800
Subject: [PATCH 9/9] Revert "arm64: dts: rockchip: add xhci trb ent quirk for
 rockchip SoCs"

This reverts commit fdc8aea2c08e122c000c3c9802b376fc1207c113.

This patch remove unused property "snps,xhci-trb-ent-quirk"
for rockchip platforms.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I849019919feecd1a35a26e5d668e53a8d8bcae2e
---
 arch/arm64/boot/dts/rockchip/rk1808.dtsi        | 1 -
 arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi | 1 -
 2 files changed, 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi
index 59e1785de7da..4ad5f039e571 100644
--- a/arch/arm64/boot/dts/rockchip/rk1808.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi
@@ -385,7 +385,6 @@
 			snps,dis_u3_susphy_quirk;
 			snps,dis-del-phy-power-chg-quirk;
 			snps,tx-ipgap-linecheck-dis-quirk;
-			snps,xhci-trb-ent-quirk;
 			snps,parkmode-disable-hs-quirk;
 			snps,parkmode-disable-ss-quirk;
 			status = "disabled";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi
index 5ad85b1679f8..4e0781ef324a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi
@@ -156,7 +156,6 @@
 			snps,dis_u3_susphy_quirk;
 			snps,dis-del-phy-power-chg-quirk;
 			snps,tx-ipgap-linecheck-dis-quirk;
-			snps,xhci-trb-ent-quirk;
 			status = "disabled";
 		};
 	};