From 2d2d364214d613d80961965a462824fa7a5ad692 Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@rock-chips.com>
Date: Tue, 11 Feb 2025 20:02:53 +0800
Subject: [PATCH] arm64: dts: rockchip: rv1126b: Add otp node

Change-Id: Ib972ea992eb2952f4c733e3a9fedd0d936cc1f87
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rv1126b.dtsi | 34 +++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
index fa5cea4d6a13..91ebf945c0e8 100644
--- a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
@@ -804,6 +804,40 @@
 		#dma-cells = <1>;
 	};
 
+	otp: otp@20b90000 {
+		compatible = "rockchip,rv1126b-otp";
+		reg = <0x20b90000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>,
+			 <&cru PCLK_OTPC_NS>, <&cru PCLK_OTP_MASK>;
+		clock-names = "usr", "sbpi", "apb", "phy";
+		resets = <&cru SRST_RESETN_USER_OTPC_NS>, <&cru SRST_RESETN_SBPI_OTPC_NS>,
+			 <&cru SRST_PRESETN_OTPC_NS>, <&cru SRST_PRESETN_OTP_MASK>;
+		reset-names = "usr", "sbpi", "apb", "phy";
+
+		/* Data cells */
+		cpu_code: cpu-code@2 {
+			reg = <0x02 0x2>;
+		};
+		cpu_version: cpu-version@21 {
+			reg = <0x21 0x1>;
+			bits = <3 3>;
+		};
+		otp_id: otp-id@22 {
+			reg = <0x22 0x10>;
+		};
+		cpu_leakage: cpu-leakage@32 {
+			reg = <0x32 0x1>;
+		};
+		log_leakage: log-leakage@33 {
+			reg = <0x33 0x1>;
+		};
+		npu_leakage: npu-leakage@34 {
+			reg = <0x34 0x1>;
+		};
+	};
+
 	tsadc: tsadc@20bb0000 {
 		compatible = "rockchip,rv1126b-tsadc";
 		reg = <0x20bb0000 0x400>;