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RK292X:add VPU dvfs
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6
arch/arm/mach-rk2928/cpufreq.c
Normal file → Executable file
6
arch/arm/mach-rk2928/cpufreq.c
Normal file → Executable file
@@ -236,6 +236,8 @@ static int rk30_cpu_init(struct cpufreq_policy *policy)
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if (policy->cpu == 0) {
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int i;
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struct clk *ddr_clk;
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struct clk *aclk_vepu_clk;
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gpu_clk = clk_get(NULL, "gpu");
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if (!IS_ERR(gpu_clk))
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clk_enable_dvfs(gpu_clk);
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@@ -277,6 +279,10 @@ static int rk30_cpu_init(struct cpufreq_policy *policy)
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clk_enable_dvfs(ddr_clk);
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}
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aclk_vepu_clk = clk_get(NULL, "aclk_vepu");
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if (!IS_ERR(aclk_vepu_clk))
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clk_enable_dvfs(aclk_vepu_clk);
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freq_wq = create_singlethread_workqueue("rk30_cpufreqd");
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#ifdef CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
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if (rk30_cpufreq_is_ondemand_policy(policy)) {
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13
arch/arm/mach-rk2928/dvfs.c
Normal file → Executable file
13
arch/arm/mach-rk2928/dvfs.c
Normal file → Executable file
@@ -1289,6 +1289,13 @@ static struct cpufreq_frequency_table peri_aclk_dvfs_table[] = {
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{.frequency = CPUFREQ_TABLE_END},
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};
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static struct cpufreq_frequency_table vpu_dvfs_table[] = {
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{.frequency = 266 * DVFS_KHZ, .index = 1100 * DVFS_MV},
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{.frequency = 300 * DVFS_KHZ, .index = 1100 * DVFS_MV},
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{.frequency = 400 * DVFS_KHZ, .index = 1200 * DVFS_MV},
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{.frequency = CPUFREQ_TABLE_END},
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};
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static struct cpufreq_frequency_table dep_cpu2core_table[] = {
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// {.frequency = 252 * DVFS_KHZ, .index = 1025 * DVFS_MV},
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// {.frequency = 504 * DVFS_KHZ, .index = 1025 * DVFS_MV},
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@@ -1413,6 +1420,11 @@ static struct pds_list aclk_periph_pds[] = {
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CLK_PDS(NULL),
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};
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static struct pds_list aclk_vepu_pds[] = {
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CLK_PDS(&pd_video),
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CLK_PDS(NULL),
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};
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#define RK_CLKS(_clk_name, _ppds, _dvfs_table, _dvfs_nb) \
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{ \
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.name = _clk_name, \
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@@ -1425,6 +1437,7 @@ static struct clk_node rk30_clks[] = {
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RK_CLKS("cpu", cpu_pds, cpu_dvfs_table, &rk_dvfs_clk_notifier),
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RK_CLKS("ddr", ddr_pds, ddr_dvfs_table, &rk_dvfs_clk_notifier),
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RK_CLKS("gpu", gpu_pds, gpu_dvfs_table, &rk_dvfs_clk_notifier),
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RK_CLKS("aclk_vepu", aclk_vepu_pds, vpu_dvfs_table, &rk_dvfs_clk_notifier),
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//RK_CLKS("aclk_periph", aclk_periph_pds, peri_aclk_dvfs_table, &rk_dvfs_clk_notifier),
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};
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