From 2e0c97d607f1ae84f0ed2cd29c7dbe4323d794cd Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Sat, 10 Feb 2018 10:33:19 +0800 Subject: [PATCH] clk: rockchip: px30: add more setting of cpu-clk Change-Id: Ie3f22964f16a636c33c5b215afb6ac8ddd653918 Signed-off-by: Liang Chen --- drivers/clk/rockchip/clk-px30.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c index 7a60c382e53f..0b010d4609ed 100644 --- a/drivers/clk/rockchip/clk-px30.c +++ b/drivers/clk/rockchip/clk-px30.c @@ -102,11 +102,22 @@ static struct rockchip_pll_rate_table px30_pll_rates[] = { static struct rockchip_cpuclk_rate_table px30_cpuclk_rates[] __initdata = { PX30_CPUCLK_RATE(1608000000, 1, 7), + PX30_CPUCLK_RATE(1584000000, 1, 7), + PX30_CPUCLK_RATE(1560000000, 1, 7), + PX30_CPUCLK_RATE(1536000000, 1, 7), PX30_CPUCLK_RATE(1512000000, 1, 7), PX30_CPUCLK_RATE(1488000000, 1, 5), + PX30_CPUCLK_RATE(1464000000, 1, 5), + PX30_CPUCLK_RATE(1440000000, 1, 5), PX30_CPUCLK_RATE(1416000000, 1, 5), PX30_CPUCLK_RATE(1392000000, 1, 5), + PX30_CPUCLK_RATE(1368000000, 1, 5), + PX30_CPUCLK_RATE(1344000000, 1, 5), + PX30_CPUCLK_RATE(1320000000, 1, 5), PX30_CPUCLK_RATE(1296000000, 1, 5), + PX30_CPUCLK_RATE(1272000000, 1, 5), + PX30_CPUCLK_RATE(1248000000, 1, 5), + PX30_CPUCLK_RATE(1224000000, 1, 5), PX30_CPUCLK_RATE(1200000000, 1, 5), PX30_CPUCLK_RATE(1104000000, 1, 5), PX30_CPUCLK_RATE(1008000000, 1, 5),