diff --git a/arch/arm/configs/rv1106-tb-nofastae.config b/arch/arm/configs/rv1106-tb-nofastae.config index ec668078748d..92e443eb8c02 100644 --- a/arch/arm/configs/rv1106-tb-nofastae.config +++ b/arch/arm/configs/rv1106-tb-nofastae.config @@ -312,7 +312,7 @@ CONFIG_MTD_SPI_NOR_MISC=y # CONFIG_PL320_MBOX is not set # CONFIG_PLATFORM_MHU is not set # CONFIG_PWRSEQ_EMMC is not set -# CONFIG_PWRSEQ_SIMPLE is not set +CONFIG_PWRSEQ_SIMPLE=y # CONFIG_RD_BZIP2 is not set # CONFIG_RD_GZIP is not set # CONFIG_RD_LZ4 is not set diff --git a/arch/arm64/boot/dts/rockchip/rk3308b-amp.dtsi b/arch/arm64/boot/dts/rockchip/rk3308b-amp.dtsi index a2d39c8ea3ee..5a4548d8149d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308b-amp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308b-amp.dtsi @@ -15,7 +15,8 @@ pinctrl-0 = <&uart1_xfer>; status = "okay"; amp-cpu-aff-maskbits = /bits/ 64 <0x0 0x1 0x1 0x2 0x2 0x4 0x3 0x8>; - amp-irqs = /bits/ 64 ; + amp-irqs = /bits/ 64 ; }; reserved-memory { @@ -28,6 +29,29 @@ reg = <0x0 0x2e00000 0x0 0x1200000>; no-map; }; + + rpmsg_reserved: rpmsg@7c00000 { + reg = <0x0 0x07c00000 0x0 0x400000>; + no-map; + }; + + rpmsg_dma_reserved: rpmsg-dma@8000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x08000000 0x0 0x100000>; + no-map; + }; + }; + + rpmsg: rpmsg@7c00000 { + compatible = "rockchip,rpmsg-softirq"; + interrupts = , + ; + rockchip,vdev-nums = <1>; + rockchip,link-id = <0x03>; + reg = <0x0 0x7c00000 0x0 0x20000>; + memory-region = <&rpmsg_dma_reserved>; + + status = "okay"; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 6f7616c99ecc..72bf632b0ff1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -3501,8 +3501,8 @@ rockchip,pvtm-temp-prop = <(-113) (-113)>; rockchip,pvtm-thermal-zone = "npu-thermal"; - clocks = <&cru PCLK_NPU_GRF>; - clock-names = "pclk"; + clocks = <&cru PCLK_NPU_GRF>, <&cru HCLK_NPU_ROOT>; + clock-names = "pclk", "hclk"; rockchip,grf = <&npu_grf>; volt-mem-read-margin = < 855000 1 diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index efcf8139dc31..af9aea4725ff 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -6328,7 +6328,8 @@ static void vop2_crtc_regs_dump(struct drm_crtc *crtc, struct seq_file *s) /* only need to dump once at first active crtc for vop2 */ for (i = 0; i < vop2_data->nr_vps; i++) { - if (vop2->vps[i].rockchip_crtc.crtc.state->active) { + if (vop2->vps[i].rockchip_crtc.crtc.state && + vop2->vps[i].rockchip_crtc.crtc.state->active) { first_active_crtc = &vop2->vps[i].rockchip_crtc.crtc; break; } @@ -6371,7 +6372,8 @@ static void vop2_crtc_active_regs_dump(struct drm_crtc *crtc, struct seq_file *s /* only need to dump once at first active crtc for vop2 */ for (i = 0; i < vop2_data->nr_vps; i++) { - if (vop2->vps[i].rockchip_crtc.crtc.state->active) { + if (vop2->vps[i].rockchip_crtc.crtc.state && + vop2->vps[i].rockchip_crtc.crtc.state->active) { first_active_crtc = &vop2->vps[i].rockchip_crtc.crtc; break; } diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c index d2cc1bdf6cf6..1a405b5aabc4 100644 --- a/drivers/pwm/pwm-rockchip.c +++ b/drivers/pwm/pwm-rockchip.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -65,6 +66,8 @@ struct rockchip_pwm_chip { struct pinctrl *pinctrl; struct pinctrl_state *active_state; const struct rockchip_pwm_data *data; + struct resource *res; + struct dentry *debugfs; void __iomem *base; unsigned long clk_rate; bool vop_pwm_en; /* indicate voppwm mirror register state */ @@ -373,6 +376,57 @@ out: return ret; } +#ifdef CONFIG_DEBUG_FS +static int rockchip_pwm_debugfs_show(struct seq_file *s, void *data) +{ + struct rockchip_pwm_chip *pc = s->private; + u32 regs_start; + int i; + int ret = 0; + + if (!pc->oneshot_en) { + ret = clk_enable(pc->pclk); + if (ret) + return ret; + } + + regs_start = (u32)pc->res->start - pc->channel_id * 0x10; + for (i = 0; i < 0x40; i += 4) { + seq_printf(s, "%08x: %08x %08x %08x %08x\n", regs_start + i * 4, + readl_relaxed(pc->base + (4 * i)), + readl_relaxed(pc->base + (4 * (i + 1))), + readl_relaxed(pc->base + (4 * (i + 2))), + readl_relaxed(pc->base + (4 * (i + 3)))); + } + + if (!pc->oneshot_en) + clk_disable(pc->pclk); + + return ret; +} +DEFINE_SHOW_ATTRIBUTE(rockchip_pwm_debugfs); + +static inline void rockchip_pwm_debugfs_init(struct rockchip_pwm_chip *pc) +{ + pc->debugfs = debugfs_create_file(dev_name(pc->chip.dev), + S_IFREG | 0444, NULL, pc, + &rockchip_pwm_debugfs_fops); +} + +static inline void rockchip_pwm_debugfs_deinit(struct rockchip_pwm_chip *pc) +{ + debugfs_remove(pc->debugfs); +} +#else +static inline void rockchip_pwm_debugfs_init(struct rockchip_pwm_chip *pc) +{ +} + +static inline void rockchip_pwm_debugfs_deinit(struct rockchip_pwm_chip *pc) +{ +} +#endif + static const struct pwm_ops rockchip_pwm_ops = { .get_state = rockchip_pwm_get_state, .apply = rockchip_pwm_apply, @@ -476,8 +530,14 @@ static int rockchip_pwm_probe(struct platform_device *pdev) return -ENOMEM; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pc->base = devm_ioremap(&pdev->dev, r->start, - resource_size(r)); + if (!r) { + dev_err(&pdev->dev, "Failed to get pwm register\n"); + return -EINVAL; + } + pc->res = r; + + pc->base = devm_ioremap(&pdev->dev, pc->res->start, + resource_size(pc->res)); if (IS_ERR(pc->base)) return PTR_ERR(pc->base); @@ -569,6 +629,8 @@ static int rockchip_pwm_probe(struct platform_device *pdev) goto err_pclk; } + rockchip_pwm_debugfs_init(pc); + /* Keep the PWM clk enabled if the PWM appears to be up and running. */ if (!enabled) clk_disable(pc->clk); @@ -591,6 +653,8 @@ static int rockchip_pwm_remove(struct platform_device *pdev) struct pwm_state state; u32 val; + rockchip_pwm_debugfs_deinit(pc); + /* * For oneshot mode, it is needed to wait for bit PWM_ENABLE * to 0, which is automatic if all periods have been sent.