From 2e4a7791147161e963b341f2d6153f7ff80c7c1a Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 28 Oct 2023 06:48:34 +0000 Subject: [PATCH] Revert "arm64: errata: Add Cortex-A520 speculative unprivileged load workaround" This reverts commit 6e3ae2927b432a3b7c8374f14dbc1bd9ebe4372c which is commit 471470bc7052d28ce125901877dd10e4c048e513 upstream. This change breaks the Android ABI, if it is needed in the future, it can be brought back in an abi-safe way. Change-Id: I1f79c77da78e5a0edde2bdebb862e4c9855175a0 Signed-off-by: Greg Kroah-Hartman --- Documentation/arm64/silicon-errata.rst | 2 -- arch/arm64/Kconfig | 13 ------------- arch/arm64/kernel/cpu_errata.c | 8 -------- arch/arm64/kernel/entry.S | 4 ---- arch/arm64/tools/cpucaps | 1 - 5 files changed, 28 deletions(-) diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index af6c549ffb1b..e252004fb8b7 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -60,8 +60,6 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A510 | #1902691 | ARM64_ERRATUM_1902691 | +----------------+-----------------+-----------------+-----------------------------+ -| ARM | Cortex-A520 | #2966298 | ARM64_ERRATUM_2966298 | -+----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 1fecc435e83c..7dafeacab872 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -972,19 +972,6 @@ config ARM64_ERRATUM_2457168 If unsure, say Y. -config ARM64_ERRATUM_2966298 - bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" - default y - help - This option adds the workaround for ARM Cortex-A520 erratum 2966298. - - On an affected Cortex-A520 core, a speculatively executed unprivileged - load might leak data from a privileged level via a cache side channel. - - Work around this problem by executing a TLBI before returning to EL0. - - If unsure, say Y. - config CAVIUM_ERRATUM_22375 bool "Cavium erratum 22375, 24313" default y diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 3f917124684c..8dbf3c21ea22 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -723,14 +723,6 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .cpu_enable = cpu_clear_bf16_from_user_emulation, }, #endif -#ifdef CONFIG_ARM64_ERRATUM_2966298 - { - .desc = "ARM erratum 2966298", - .capability = ARM64_WORKAROUND_2966298, - /* Cortex-A520 r0p0 - r0p1 */ - ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A520, 0, 0, 1), - }, -#endif #ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38 { .desc = "AmpereOne erratum AC03_CPU_38", diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index de16fa917e1b..beb4db21c89c 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -419,10 +419,6 @@ alternative_else_nop_endif ldp x28, x29, [sp, #16 * 14] .if \el == 0 -alternative_if ARM64_WORKAROUND_2966298 - tlbi vale1, xzr - dsb nsh -alternative_else_nop_endif alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 ldr lr, [sp, #S_LR] add sp, sp, #PT_REGS_SIZE // restore sp diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index e77c6cd855b8..7b79a8b09504 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -71,7 +71,6 @@ WORKAROUND_2064142 WORKAROUND_2077057 WORKAROUND_2457168 WORKAROUND_2658417 -WORKAROUND_2966298 WORKAROUND_TRBE_OVERWRITE_FILL_MODE WORKAROUND_TSB_FLUSH_FAILURE WORKAROUND_TRBE_WRITE_OUT_OF_RANGE