From 2e790a5e280729cfbc4207fbc362d91b466b9510 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Wed, 9 Oct 2019 21:24:50 +0200 Subject: [PATCH] [riscv64] Clear load reservations while restoring hart contexts. --- debian/changelog | 1 + ...d-reservations-while-restoring-hart-.patch | 64 +++++++++++++++++++ debian/patches/series | 1 + 3 files changed, 66 insertions(+) create mode 100644 debian/patches/bugfix/riscv64/RISC-V-Clear-load-reservations-while-restoring-hart-.patch diff --git a/debian/changelog b/debian/changelog index 1f34fd180d2f..c98f66d7010e 100644 --- a/debian/changelog +++ b/debian/changelog @@ -10,6 +10,7 @@ linux (5.3.2-1~exp2) UNRELEASED; urgency=medium * [riscv64] Enable MMC, MMC_SPI. * [riscv64] udeb: Add mmc-core-modules and mmc-modules. * [riscv64] Fix memblock reservation for device tree blob. + * [riscv64] Clear load reservations while restoring hart contexts. [ Ben Hutchings ] * [mips*] Revert "Only define MAX_PHYSMEM_BITS on Loongson-3" diff --git a/debian/patches/bugfix/riscv64/RISC-V-Clear-load-reservations-while-restoring-hart-.patch b/debian/patches/bugfix/riscv64/RISC-V-Clear-load-reservations-while-restoring-hart-.patch new file mode 100644 index 000000000000..675c377a0128 --- /dev/null +++ b/debian/patches/bugfix/riscv64/RISC-V-Clear-load-reservations-while-restoring-hart-.patch @@ -0,0 +1,64 @@ +From: Palmer Dabbelt +Date: Tue, 24 Sep 2019 17:15:56 -0700 +Subject: RISC-V: Clear load reservations while restoring hart contexts +Origin: https://git.kernel.org/linus/18856604b3e7090ce42d533995173ee70c24b1c9 + +This is almost entirely a comment. The bug is unlikely to manifest on +existing hardware because there is a timeout on load reservations, but +manifests on QEMU because there is no timeout. + +Signed-off-by: Palmer Dabbelt +Reviewed-by: Christoph Hellwig +Signed-off-by: Paul Walmsley +--- + arch/riscv/include/asm/asm.h | 1 + + arch/riscv/kernel/entry.S | 21 ++++++++++++++++++++- + 2 files changed, 21 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h +index 5a02b7d50940..9c992a88d858 100644 +--- a/arch/riscv/include/asm/asm.h ++++ b/arch/riscv/include/asm/asm.h +@@ -22,6 +22,7 @@ + + #define REG_L __REG_SEL(ld, lw) + #define REG_S __REG_SEL(sd, sw) ++#define REG_SC __REG_SEL(sc.d, sc.w) + #define SZREG __REG_SEL(8, 4) + #define LGREG __REG_SEL(3, 2) + +diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S +index da7aa88113c2..2d592da1e776 100644 +--- a/arch/riscv/kernel/entry.S ++++ b/arch/riscv/kernel/entry.S +@@ -98,7 +98,26 @@ _save_context: + */ + .macro RESTORE_ALL + REG_L a0, PT_SSTATUS(sp) +- REG_L a2, PT_SEPC(sp) ++ /* ++ * The current load reservation is effectively part of the processor's ++ * state, in the sense that load reservations cannot be shared between ++ * different hart contexts. We can't actually save and restore a load ++ * reservation, so instead here we clear any existing reservation -- ++ * it's always legal for implementations to clear load reservations at ++ * any point (as long as the forward progress guarantee is kept, but ++ * we'll ignore that here). ++ * ++ * Dangling load reservations can be the result of taking a trap in the ++ * middle of an LR/SC sequence, but can also be the result of a taken ++ * forward branch around an SC -- which is how we implement CAS. As a ++ * result we need to clear reservations between the last CAS and the ++ * jump back to the new context. While it is unlikely the store ++ * completes, implementations are allowed to expand reservations to be ++ * arbitrarily large. ++ */ ++ REG_L a2, PT_SEPC(sp) ++ REG_SC x0, a2, PT_SEPC(sp) ++ + csrw CSR_SSTATUS, a0 + csrw CSR_SEPC, a2 + +-- +2.23.0 + diff --git a/debian/patches/series b/debian/patches/series index 872781f9fd9b..972d32ce347a 100644 --- a/debian/patches/series +++ b/debian/patches/series @@ -72,6 +72,7 @@ bugfix/powerpc/powerpc-boot-fix-missing-crc32poly.h-when-building-with-kernel_xz bugfix/arm64/arm64-acpi-Add-fixup-for-HPE-m400-quirks.patch bugfix/x86/x86-32-disable-3dnow-in-generic-config.patch bugfix/riscv64/riscv-Fix-memblock-reservation-for-device-tree-blob.patch +bugfix/riscv64/RISC-V-Clear-load-reservations-while-restoring-hart-.patch # Arch features features/mips/MIPS-Loongson-3-Add-Loongson-LS3A-RS780E-1-way-machi.patch