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drm/amd/display: Fix tiled display misalignment

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[ Upstream commit c4b8394e76adba4f50a3c2696c75b214a291e24a ]

[Why]
When otg workaround is applied during clock update, otgs of
tiled display went out of sync.

[How]
To call dc_trigger_sync() after clock update to sync otgs again.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Meenakshikumar Somasundaram
2023-11-09 00:04:36 -05:00
committed by Greg Kroah-Hartman
parent f217be126a
commit 2ed3db8991
1 changed files with 4 additions and 0 deletions
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4
drivers/gpu/drm/amd/display/dc/core/dc.c
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@@ -1680,6 +1680,10 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
wait_for_no_pipes_pending(dc, context); wait_for_no_pipes_pending(dc, context);
/* pplib is notified if disp_num changed */ /* pplib is notified if disp_num changed */
dc->hwss.optimize_bandwidth(dc, context); dc->hwss.optimize_bandwidth(dc, context);
/* Need to do otg sync again as otg could be out of sync due to otg
* workaround applied during clock update
*/
dc_trigger_sync(dc, context);
} }
if (dc->ctx->dce_version >= DCE_VERSION_MAX) if (dc->ctx->dce_version >= DCE_VERSION_MAX)