diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 9ba38641b31f..585b24e28bdf 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include @@ -187,6 +188,20 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd) .keepon_startup = keepon, \ } +#define DOMAIN_M_A(pwr, status, req, idle, ack, always, wakeup, keepon) \ +{ \ + .pwr_w_mask = (pwr) << 16, \ + .pwr_mask = (pwr), \ + .status_mask = (status), \ + .req_w_mask = (req) << 16, \ + .req_mask = (req), \ + .idle_mask = (idle), \ + .ack_mask = (ack), \ + .always_on = always, \ + .active_wakeup = wakeup, \ + .keepon_startup = keepon, \ +} + #define DOMAIN_M_O(_name, pwr, status, p_offset, req, idle, ack, r_offset, wakeup, keepon) \ { \ .name = _name, \ @@ -268,6 +283,9 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd) #define DOMAIN_RK3399_PROTECT(name, pwr, status, req, wakeup) \ DOMAIN(name, pwr, status, req, req, req, wakeup, true) +#define DOMAIN_RK3528(pwr, req, always, wakeup) \ + DOMAIN_M_A(pwr, pwr, req, req, req, always, wakeup, false) + #define DOMAIN_RK3568(name, pwr, req, wakeup) \ DOMAIN_M(name, pwr, pwr, req, req, req, wakeup, false) @@ -1539,6 +1557,18 @@ static const struct rockchip_domain_info rk3399_pm_domains[] = { [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), }; +static const struct rockchip_domain_info rk3528_pm_domains[] = { + [RK3528_PD_PMU] = DOMAIN_RK3528(0, BIT(0), true, false), + [RK3528_PD_BUS] = DOMAIN_RK3528(0, BIT(1), true, false), + [RK3528_PD_DDR] = DOMAIN_RK3528(0, BIT(2), true, false), + [RK3528_PD_MSCH] = DOMAIN_RK3528(0, BIT(3), true, false), + [RK3528_PD_GPU] = DOMAIN_RK3528(BIT(0), BIT(4), true, false), + [RK3528_PD_RKVDEC] = DOMAIN_RK3528(0, BIT(5), true, false), + [RK3528_PD_RKVENC] = DOMAIN_RK3528(0, BIT(6), true, false), + [RK3528_PD_VO] = DOMAIN_RK3528(0, BIT(7), true, false), + [RK3528_PD_VPU] = DOMAIN_RK3528(0, BIT(8), true, false), +}; + static const struct rockchip_domain_info rk3568_pm_domains[] = { [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false), [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false), @@ -1741,6 +1771,17 @@ static const struct rockchip_pmu_info rk3399_pmu = { .domain_info = rk3399_pm_domains, }; +static const struct rockchip_pmu_info rk3528_pmu = { + .pwr_offset = 0x1210, + .status_offset = 0x1230, + .req_offset = 0x1110, + .idle_offset = 0x1128, + .ack_offset = 0x1120, + + .num_domains = ARRAY_SIZE(rk3528_pm_domains), + .domain_info = rk3528_pm_domains, +}; + static const struct rockchip_pmu_info rk3568_pmu = { .pwr_offset = 0xa0, .status_offset = 0x98, @@ -1820,6 +1861,12 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = { .compatible = "rockchip,rk3399-power-controller", .data = (void *)&rk3399_pmu, }, +#ifdef CONFIG_CPU_RK3528 + { + .compatible = "rockchip,rk3528-power-controller", + .data = (void *)&rk3528_pmu, + }, +#endif { .compatible = "rockchip,rk3568-power-controller", .data = (void *)&rk3568_pmu,