From 2f5fe2c0bbd4fa95102aadd60da1100989103aa0 Mon Sep 17 00:00:00 2001 From: Yifeng Zhao Date: Sat, 3 Sep 2022 09:38:00 +0800 Subject: [PATCH] phy: rockchip: naneng-combophy: config sata2 rate to 6G for rk3588 Fixes: 1a6396458b85 ("phy: rockchip: naneng-combphy: add support rk3588") Signed-off-by: Yifeng Zhao Change-Id: I9ca63ea12d1b08e8aac5ecb439b4ee1516f11768 --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 84c3884f5cff..6f7aa8ebc292 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -869,7 +869,7 @@ static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, /* pipe-grf */ .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, - .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, + .pipe_con1_for_sata = { 0x0004, 2, 0, 0x00, 0x2 }, }; static const struct clk_bulk_data rk3588_clks[] = {