From 3089a1c4969953c35ba63582cc7f63e8f2dbccfc Mon Sep 17 00:00:00 2001 From: Suzuki K Poulose Date: Wed, 24 Feb 2021 23:58:44 +0000 Subject: [PATCH] FROMLIST: arm64: Add support for trace synchronization barrier tsb csync synchronizes the trace operation of instructions. The instruction is a nop when FEAT_TRF is not implemented. Bug: 174685394 Cc: Mathieu Poirier Cc: Mike Leach Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Suzuki K Poulose Signed-off-by: Anshuman Khandual Link: https://lore.kernel.org/linux-arm-kernel/20210225193543.2920532-7-suzuki.poulose@arm.com/ Signed-off-by: Qais Yousef Change-Id: I36f91c3d9d2b1abeeabcb2c4f05e9eccaefae8ac --- arch/arm64/include/asm/barrier.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index c3009b0e5239..5a8367a2b868 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -23,6 +23,7 @@ #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define psb_csync() asm volatile("hint #17" : : : "memory") +#define tsb_csync() asm volatile("hint #18" : : : "memory") #define csdb() asm volatile("hint #20" : : : "memory") #define spec_bar() asm volatile(ALTERNATIVE("dsb nsh\nisb\n", \