From 30a5909fa72de2f9e086e23a1bcaab09bfbd3e2e Mon Sep 17 00:00:00 2001 From: Zhe Wang Date: Fri, 5 Apr 2019 14:42:48 +0800 Subject: [PATCH] audio: TM2 audio basic function bringup [1/1] PD#SWPL-6721 Problem: TM2 bringup Solution: audio basic function bringup Verify: Verified on T962e2_ab311 Change-Id: Ic48ded3964ea87e40c4d683d71a50bbdc1975f91 Signed-off-by: Zhe Wang Conflicts: arch/arm64/boot/dts/amlogic/tm2_t962x3_ab301.dts --- MAINTAINERS | 1 - arch/arm/boot/dts/amlogic/mesontl1.dtsi | 2083 ----------------- .../dt-bindings/clock/amlogic,tm2-audio-clk.h | 97 + sound/soc/amlogic/auge/Makefile | 1 + sound/soc/amlogic/auge/audio_clks.c | 4 + sound/soc/amlogic/auge/audio_clks.h | 1 + sound/soc/amlogic/auge/audio_controller.c | 1 + sound/soc/amlogic/auge/card.c | 9 +- sound/soc/amlogic/auge/ddr_mngr.c | 6 +- sound/soc/amlogic/auge/earc.c | 5 +- sound/soc/amlogic/auge/pdm_match_table.c | 10 + sound/soc/amlogic/auge/spdif_match_table.c | 22 + sound/soc/amlogic/auge/tdm_match_table.c | 36 + sound/soc/amlogic/auge/tm2,clocks.c | 392 ++++ 14 files changed, 577 insertions(+), 2091 deletions(-) delete mode 100644 arch/arm/boot/dts/amlogic/mesontl1.dtsi create mode 100644 include/dt-bindings/clock/amlogic,tm2-audio-clk.h create mode 100644 sound/soc/amlogic/auge/tm2,clocks.c diff --git a/MAINTAINERS b/MAINTAINERS index 2d19e1dfd773..ae6f0d4a5b79 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14430,7 +14430,6 @@ F: include/linux/amlogic/meson_cooldev.h AMLOGIC G12A Audio DRIVER M: Xing Wang F: sound/soc/amlogic/auge/* -F: sound/soc/codec/amlogic/* AMLOGIC G12A BL_EXTERN LP8556 DRIVER M: Weiming Liu diff --git a/arch/arm/boot/dts/amlogic/mesontl1.dtsi b/arch/arm/boot/dts/amlogic/mesontl1.dtsi deleted file mode 100644 index e08b0710512a..000000000000 --- a/arch/arm/boot/dts/amlogic/mesontl1.dtsi +++ /dev/null @@ -1,2083 +0,0 @@ -/* - * arch/arm/boot/dts/amlogic/mesontl1.dtsi - * - * Copyright (C) 2018 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "mesong12a-bifrost.dtsi" - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus:cpus { - #address-cells = <1>; - #size-cells = <0>; - #cooling-cells = <2>;/* min followed by max */ - CPU0:cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x0>; - //timer=<&timer_a>; - enable-method = "psci"; - clocks = <&clkc CLKID_CPU_CLK>, - <&clkc CLKID_CPU_FCLK_P>, - <&clkc CLKID_SYS_PLL>; - clock-names = "core_clk", - "low_freq_clk_parent", - "high_freq_clk_parent"; - operating-points-v2 = <&cpu_opp_table0>; - cpu-supply = <&vddcpu0>; - //cpu-idle-states = <&SYSTEM_SLEEP_0>; - }; - - CPU1:cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x1>; - //timer=<&timer_b>; - enable-method = "psci"; - clocks = <&clkc CLKID_CPU_CLK>, - <&clkc CLKID_CPU_FCLK_P>, - <&clkc CLKID_SYS_PLL>; - clock-names = "core_clk", - "low_freq_clk_parent", - "high_freq_clk_parent"; - operating-points-v2 = <&cpu_opp_table0>; - cpu-supply = <&vddcpu0>; - //cpu-idle-states = <&SYSTEM_SLEEP_0>; - }; - - CPU2:cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x2>; - //timer=<&timer_c>; - enable-method = "psci"; - clocks = <&clkc CLKID_CPU_CLK>, - <&clkc CLKID_CPU_FCLK_P>, - <&clkc CLKID_SYS_PLL>; - clock-names = "core_clk", - "low_freq_clk_parent", - "high_freq_clk_parent"; - operating-points-v2 = <&cpu_opp_table0>; - cpu-supply = <&vddcpu0>; - //cpu-idle-states = <&SYSTEM_SLEEP_0>; - }; - - CPU3:cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x0 0x3>; - //timer=<&timer_d>; - enable-method = "psci"; - clocks = <&clkc CLKID_CPU_CLK>, - <&clkc CLKID_CPU_FCLK_P>, - <&clkc CLKID_SYS_PLL>; - clock-names = "core_clk", - "low_freq_clk_parent", - "high_freq_clk_parent"; - operating-points-v2 = <&cpu_opp_table0>; - cpu-supply = <&vddcpu0>; - //cpu-idle-states = <&SYSTEM_SLEEP_0>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - timer_bc { - compatible = "arm, meson-bc-timer"; - reg = <0xffd0f190 0x4 0xffd0f194 0x4>; - timer_name = "Meson TimerF"; - clockevent-rating =<300>; - clockevent-shift =<20>; - clockevent-features =<0x23>; - interrupts = <0 60 1>; - bit_enable =<16>; - bit_mode =<12>; - bit_resolution =<0>; - }; - - arm_pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = ; - reg = <0xff634400 0x1000>; - - /* addr = base + offset << 2 */ - sys_cpu_status0_offset = <0xa0>; - - sys_cpu_status0_pmuirq_mask = <0xf>; - - /* default 10ms */ - relax_timer_ns = <10000000>; - - /* default 10000us */ - max_wait_cnt = <10000>; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0xffc01000 0x1000>, - <0xffc02000 0x0100>; - interrupts = ; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - scpi_clocks { - compatible = "arm, scpi-clks"; - - scpi_dvfs: scpi_clocks@0 { - compatible = "arm, scpi-clk-indexed"; - #clock-cells = <1>; - clock-indices = <0>; - clock-output-names = "vcpu"; - }; - }; - - secmon { - compatible = "amlogic, secmon"; - memory-region = <&secmon_reserved>; - in_base_func = <0x82000020>; - out_base_func = <0x82000021>; - reserve_mem_size = <0x00300000>; - }; - - securitykey { - compatible = "amlogic, securitykey"; - status = "okay"; - storage_query = <0x82000060>; - storage_read = <0x82000061>; - storage_write = <0x82000062>; - storage_tell = <0x82000063>; - storage_verify = <0x82000064>; - storage_status = <0x82000065>; - storage_list = <0x82000067>; - storage_remove = <0x82000068>; - storage_in_func = <0x82000023>; - storage_out_func = <0x82000024>; - storage_block_func = <0x82000025>; - storage_size_func = <0x82000027>; - storage_set_enctype = <0x8200006A>; - storage_get_enctype = <0x8200006B>; - storage_version = <0x8200006C>; - }; - - mailbox: mhu@ff63c400 { - compatible = "amlogic, meson_mhu"; - reg = <0xff63c400 0x4c>, /* MHU registers */ - <0xfffd7000 0x800>; /* Payload area */ - interrupts = <0 209 1>, /* low priority interrupt */ - <0 210 1>; /* high priority interrupt */ - #mbox-cells = <1>; - mbox-names = "cpu_to_scp_low", "cpu_to_scp_high"; - mboxes = <&mailbox 0 &mailbox 1>; - }; - - cpu_iomap { - compatible = "amlogic, iomap"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - io_cbus_base { - reg = <0xffd00000 0x101000>; - }; - io_apb_base { - reg = <0xffe01000 0x19f000>; - }; - io_aobus_base { - reg = <0xff800000 0x100000>; - }; - io_vapb_base { - reg = <0xff900000 0x200000>; - }; - io_hiu_base { - reg = <0xff63c000 0x2000>; - }; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; - - meson_suspend: pm { - compatible = "amlogic, pm"; - /*gxbaby-suspend;*/ - status = "okay"; - reg = <0xff8000a8 0x4>, - <0xff80023c 0x4>; - }; - - cpuinfo { - compatible = "amlogic, cpuinfo"; - status = "okay"; - cpuinfo_cmd = <0x82000044>; - }; - - reboot { - compatible = "amlogic,reboot"; - sys_reset = <0x84000009>; - sys_poweroff = <0x84000008>; - }; - - ram-dump { - compatible = "amlogic, ram_dump"; - status = "okay"; - }; - - securitykey { - compatible = "amlogic, securitykey"; - status = "okay"; - storage_query = <0x82000060>; - storage_read = <0x82000061>; - storage_write = <0x82000062>; - storage_tell = <0x82000063>; - storage_verify = <0x82000064>; - storage_status = <0x82000065>; - storage_list = <0x82000067>; - storage_remove = <0x82000068>; - storage_in_func = <0x82000023>; - storage_out_func = <0x82000024>; - storage_block_func = <0x82000025>; - storage_size_func = <0x82000027>; - storage_set_enctype = <0x8200006A>; - storage_get_enctype = <0x8200006B>; - storage_version = <0x8200006C>; - }; - - vpu { - compatible = "amlogic, vpu-tl1"; - status = "okay"; - clocks = <&clkc CLKID_VAPB_MUX>, - <&clkc CLKID_VPU_INTR>, - <&clkc CLKID_VPU_P0_COMP>, - <&clkc CLKID_VPU_P1_COMP>, - <&clkc CLKID_VPU_MUX>; - clock-names = "vapb_clk", - "vpu_intr_gate", - "vpu_clk0", - "vpu_clk1", - "vpu_clk"; - clk_level = <7>; - /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ - /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ - }; - - ethmac: ethernet@ff3f0000 { - compatible = "amlogic, g12a-eth-dwmac","snps,dwmac"; - reg = <0xff3f0000 0x10000 - 0xff634540 0x8 - 0xff64c000 0xa0>; - reg-names = "eth_base", "eth_cfg", "eth_pll"; - interrupts = <0 8 1>; - interrupt-names = "macirq"; - status = "disabled"; - clocks = <&clkc CLKID_ETH_CORE>; - clock-names = "ethclk81"; - pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; - analog_val = <0x20200000 0x0000c000 0x00000023>; - }; - - pinctrl_aobus: pinctrl@ff800014 { - compatible = "amlogic,meson-tl1-aobus-pinctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio_ao: ao-bank@ff800014 { - reg = <0xff800014 0x8>, - <0xff800024 0x14>, - <0xff80001c 0x8>; - reg-names = "mux", "gpio", "drive-strength"; - gpio-controller; - #gpio-cells = <2>; - }; - - aoceca_mux:aoceca_mux { - mux { - groups = "cec_ao_a"; - function = "cec_ao"; - }; - }; - - aocecb_mux:aocecb_mux { - mux { - groups = "cec_ao_b"; - function = "cec_ao"; - }; - }; - }; - - pinctrl_periphs: pinctrl@ff6346c0 { - compatible = "amlogic,meson-tl1-periphs-pinctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio: banks@ff6346c0 { - reg = <0xff6346c0 0x40>, - <0xff6344e8 0x18>, - <0xff634520 0x18>, - <0xff634440 0x4c>, - <0xff634740 0x1c>; - reg-names = "mux", - "pull", - "pull-enable", - "gpio", - "drive-strength"; - gpio-controller; - #gpio-cells = <2>; - }; - - - hdmirx_a_mux:hdmirx_a_mux { - mux { - groups = "hdmirx_a_hpd", "hdmirx_a_det", - "hdmirx_a_sda", "hdmirx_a_sck"; - function = "hdmirx_a"; - }; - }; - - hdmirx_b_mux:hdmirx_b_mux { - mux { - groups = "hdmirx_b_hpd", "hdmirx_b_det", - "hdmirx_b_sda", "hdmirx_b_sck"; - function = "hdmirx_b"; - }; - }; - - hdmirx_c_mux:hdmirx_c_mux { - mux { - groups = "hdmirx_c_hpd", "hdmirx_c_det", - "hdmirx_c_sda", "hdmirx_c_sck"; - function = "hdmirx_c"; - }; - }; - - }; - - dwc3: dwc3@ff500000 { - compatible = "synopsys, dwc3"; - status = "disabled"; - reg = <0xff500000 0x100000>; - interrupts = <0 30 4>; - usb-phy = <&usb2_phy_v2>, <&usb3_phy_v2>; - cpu-type = "gxl"; - clock-src = "usb3.0"; - clocks = <&clkc CLKID_USB_GENERAL>; - clock-names = "dwc_general"; - }; - - usb2_phy_v2: usb2phy@ffe09000 { - compatible = "amlogic, amlogic-new-usb2-v2"; - status = "disabled"; - reg = <0xffe09000 0x80 - 0xffd01008 0x100 - 0xff636000 0x2000 - 0xff63a000 0x2000 - 0xff658000 0x2000>; - pll-setting-1 = <0x09400414>; - pll-setting-2 = <0x927E0000>; - pll-setting-3 = <0xac5f69e5>; - pll-setting-4 = <0xfe18>; - pll-setting-5 = <0x8000fff>; - pll-setting-6 = <0x78000>; - pll-setting-7 = <0xe0004>; - pll-setting-8 = <0xe000c>; - version = <1>; - }; - - usb3_phy_v2: usb3phy@ffe09080 { - compatible = "amlogic, amlogic-new-usb3-v2"; - status = "disabled"; - reg = <0xffe09080 0x20>; - phy-reg = <0xff646000>; - phy-reg-size = <0x2000>; - usb2-phy-reg = <0xffe09000>; - usb2-phy-reg-size = <0x80>; - interrupts = <0 16 4>; - }; - - dwc2_a: dwc2_a@ff400000 { - compatible = "amlogic, dwc2"; - status = "disabled"; - device_name = "dwc2_a"; - reg = <0xff400000 0x40000>; - interrupts = <0 31 4>; - pl-periph-id = <0>; /** lm name */ - clock-src = "usb0"; /** clock src */ - port-id = <0>; /** ref to mach/usb.h */ - port-type = <2>; /** 0: otg, 1: host, 2: slave */ - port-speed = <0>; /** 0: default, high, 1: full */ - port-config = <0>; /** 0: default */ - /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/ - port-dma = <0>; - port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ - usb-fifo = <728>; - cpu-type = "v2"; - phy-reg = <0xffe09000>; - phy-reg-size = <0xa0>; - /** phy-interface: 0x0: amlogic-v1 phy, 0x1: synopsys phy **/ - /** 0x2: amlogic-v2 phy **/ - phy-interface = <0x2>; - clocks = <&clkc CLKID_USB_GENERAL - &clkc CLKID_USB1_TO_DDR>; - clock-names = "usb_general", - "usb1"; - }; - - wdt: watchdog@0xffd0f0d0 { - compatible = "amlogic,meson-tl1-wdt"; - status = "okay"; - reg = <0xffd0f0d0 0x10>; - clock-names = "xtal"; - clocks = <&xtal>; - }; - - jtag { - compatible = "amlogic, jtag"; - status = "disabled"; - select = "apao"; /* disable/apao/apee */ - jtagao-gpios = <&gpio_ao GPIOAO_6 0 - &gpio_ao GPIOAO_7 0 - &gpio_ao GPIOAO_8 0 - &gpio_ao GPIOAO_9 0>; - jtagee-gpios = <&gpio GPIOC_0 0 - &gpio GPIOC_1 0 - &gpio GPIOC_4 0 - &gpio GPIOC_5 0>; - }; - - saradc:saradc { - compatible = "amlogic,meson-g12a-saradc"; - status = "disabled"; - #io-channel-cells = <1>; - clocks = <&xtal>, <&clkc CLKID_SARADC_GATE>; - clock-names = "xtal", "saradc_clk"; - interrupts = ; - reg = <0xff809000 0x48>; - }; - - vddcpu0: pwmao_d-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm_AO_cd MESON_PWM_1 1250 0>; - regulator-name = "vddcpu0"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1021000>; - regulator-always-on; - max-duty-cycle = <1250>; - /* Voltage Duty-Cycle */ - voltage-table = <1021000 0>, - <1011000 3>, - <1001000 6>, - <991000 10>, - <981000 13>, - <971000 16>, - <961000 20>, - <951000 23>, - <941000 26>, - <931000 30>, - <921000 33>, - <911000 36>, - <901000 40>, - <891000 43>, - <881000 46>, - <871000 50>, - <861000 53>, - <851000 56>, - <841000 60>, - <831000 63>, - <821000 67>, - <811000 70>, - <801000 73>, - <791000 76>, - <781000 80>, - <771000 83>, - <761000 86>, - <751000 90>, - <741000 93>, - <731000 96>, - <721000 100>; - status = "okay"; - }; - - aml_dma { - compatible = "amlogic,aml_txlx_dma"; - reg = <0xff63e000 0x48>; - interrupts = <0 180 1>; - - aml_aes { - compatible = "amlogic,aes_g12a_dma"; - dev_name = "aml_aes_dma"; - status = "okay"; - }; - - aml_sha { - compatible = "amlogic,sha_dma"; - dev_name = "aml_sha_dma"; - status = "okay"; - }; - }; - - rng { - compatible = "amlogic,meson-rng"; - status = "okay"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xff630218 0x4>; - quality = /bits/ 16 <1000>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - hiubus: hiubus@ff63c000 { - compatible = "simple-bus"; - reg = <0xff63c000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xff63c000 0x2000>; - - clkc: clock-controller@0 { - compatible = "amlogic,tl1-clkc"; - #clock-cells = <1>; - reg = <0x0 0x3fc>; - }; - };/* end of hiubus*/ - - audiobus: audiobus@0xff600000 { - compatible = "amlogic, audio-controller", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xff600000 0x10000>; - ranges = <0x0 0xff600000 0x10000>; - - clkaudio:audio_clocks { - compatible = "amlogic, tl1-audio-clocks"; - #clock-cells = <1>; - reg = <0x0 0xb0>; - }; - - ddr_manager { - compatible = "amlogic, tl1-audio-ddr-manager"; - interrupts = < - GIC_SPI 148 IRQ_TYPE_EDGE_RISING - GIC_SPI 149 IRQ_TYPE_EDGE_RISING - GIC_SPI 150 IRQ_TYPE_EDGE_RISING - GIC_SPI 48 IRQ_TYPE_EDGE_RISING - GIC_SPI 152 IRQ_TYPE_EDGE_RISING - GIC_SPI 153 IRQ_TYPE_EDGE_RISING - GIC_SPI 154 IRQ_TYPE_EDGE_RISING - GIC_SPI 49 IRQ_TYPE_EDGE_RISING - >; - interrupt-names = - "toddr_a", "toddr_b", "toddr_c", - "toddr_d", - "frddr_a", "frddr_b", "frddr_c", - "frddr_d"; - }; - };/* end of audiobus*/ - - /* Sound iomap */ - aml_snd_iomap { - compatible = "amlogic, snd-iomap"; - status = "okay"; - #address-cells=<1>; - #size-cells=<1>; - ranges; - pdm_bus { - reg = <0xFF601000 0x400>; - }; - audiobus_base { - reg = <0xFF600000 0x1000>; - }; - audiolocker_base { - reg = <0xFF601400 0x400>; - }; - eqdrc_base { - reg = <0xFF602000 0x2000>; - }; - reset_base { - reg = <0xFFD01000 0x1000>; - }; - vad_base { - reg = <0xFF601800 0x800>; - }; - }; - - cbus: cbus@ffd00000 { - compatible = "simple-bus"; - reg = <0xffd00000 0x27000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xffd00000 0x27000>; - - clk-measure@18004 { - compatible = "amlogic,tl1-measure"; - reg = <0x18004 0x4 0x1800c 0x4>; - }; - - i2c0: i2c@1f000 { - compatible = "amlogic,meson-i2c"; - status = "disabled"; - reg = <0x1f000 0x20>; - interrupts = , - ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - clock-frequency = <100000>; - }; - - i2c1: i2c@1e000 { - compatible = "amlogic,meson-i2c"; - status = "disabled"; - reg = <0x1e000 0x20>; - interrupts = , - ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - clock-frequency = <100000>; - }; - - i2c2: i2c@1d000 { - compatible = "amlogic,meson-i2c"; - status = "disabled"; - reg = <0x1d000 0x20>; - interrupts = , - ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - clock-frequency = <100000>; - }; - - i2c3: i2c@1c000 { - compatible = "amlogic,meson-i2c"; - status = "disabled"; - reg = <0x1c000 0x20>; - interrupts = , - ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - clock-frequency = <100000>; - }; - - gpio_intc: interrupt-controller@f080 { - compatible = "amlogic,meson-gpio-intc", - "amlogic,meson-tl1-gpio-intc"; - reg = <0xf080 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - amlogic,channel-interrupts = - <64 65 66 67 68 69 70 71>; - status = "okay"; - }; - - pwm_ab: pwm@1b000 { - compatible = "amlogic,tl1-ee-pwm"; - reg = <0x1b000 0x20>; - #pwm-cells = <3>; - clocks = <&xtal>, - <&xtal>, - <&xtal>, - <&xtal>; - clock-names = "clkin0", - "clkin1", - "clkin2", - "clkin3"; - /* default xtal 24m clkin0-clkin2 and - * clkin1-clkin3 should be set the same - */ - status = "disabled"; - }; - - pwm_cd: pwm@1a000 { - compatible = "amlogic,tl1-ee-pwm"; - reg = <0x1a000 0x20>; - #pwm-cells = <3>; - clocks = <&xtal>, - <&xtal>, - <&xtal>, - <&xtal>; - clock-names = "clkin0", - "clkin1", - "clkin2", - "clkin3"; - status = "disabled"; - }; - - pwm_ef: pwm@19000 { - compatible = "amlogic,tl1-ee-pwm"; - reg = <0x19000 0x20>; - #pwm-cells = <3>; - clocks = <&xtal>, - <&xtal>, - <&xtal>, - <&xtal>; - clock-names = "clkin0", - "clkin1", - "clkin2", - "clkin3"; - status = "disabled"; - }; - - spicc0: spi@13000 { - compatible = "amlogic,meson-tl1-spicc", - "amlogic,meson-g12a-spicc"; - reg = <0x13000 0x44>; - interrupts = ; - clocks = <&clkc CLKID_SPICC0>, - <&clkc CLKID_SPICC0_COMP>; - clock-names = "core", "comp"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spicc1: spi@15000 { - compatible = "amlogic,meson-tl1-spicc", - "amlogic,meson-g12a-spicc"; - reg = <0x15000 0x44>; - interrupts = ; - clocks = <&clkc CLKID_SPICC1>, - <&clkc CLKID_SPICC1_COMP>; - clock-names = "core", "comp"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - aobus: aobus@ff800000 { - compatible = "simple-bus"; - reg = <0xff800000 0xb000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xff800000 0xb000>; - - cpu_version { - reg = <0x220 0x4>; - }; - - aoclkc: clock-controller@0 { - compatible = "amlogic,tl1-aoclkc"; - #clock-cells = <1>; - reg = <0x0 0x1000>; - }; - - pwm_AO_ab: pwm@7000 { - compatible = "amlogic,tl1-ao-pwm"; - reg = <0x7000 0x20>; - #pwm-cells = <3>; - clocks = <&xtal>, - <&xtal>, - <&xtal>, - <&xtal>; - clock-names = "clkin0", - "clkin1", - "clkin2", - "clkin3"; - status = "disabled"; - }; - - pwm_AO_cd: pwm@2000 { - compatible = "amlogic,tl1-ao-pwm"; - reg = <0x2000 0x20>; - #pwm-cells = <3>; - clocks = <&xtal>, - <&xtal>, - <&xtal>, - <&xtal>; - clock-names = "clkin0", - "clkin1", - "clkin2", - "clkin3"; - status = "disabled"; - }; - - uart_AO: serial@3000 { - compatible = "amlogic, meson-uart"; - reg = <0x3000 0x18>; - interrupts = <0 193 1>; - status = "okay"; - clocks = <&xtal>; - clock-names = "clk_uart"; - xtal_tick_en = <2>; - fifosize = < 64 >; - //pinctrl-names = "default"; - //pinctrl-0 = <&ao_a_uart_pins>; - /* 0 not support; 1 support */ - support-sysrq = <0>; - }; - - uart_AO_B: serial@4000 { - compatible = "amlogic, meson-uart"; - reg = <0x4000 0x18>; - interrupts = <0 197 1>; - status = "disabled"; - clocks = <&xtal>; - clock-names = "clk_uart"; - fifosize = < 64 >; - pinctrl-names = "default"; - pinctrl-0 = <&ao_b_uart_pins1>; - }; - - remote: rc@8040 { - compatible = "amlogic, aml_remote"; - reg = <0x8040 0x44>, - <0x8000 0x20>; - status = "okay"; - protocol = ; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&remote_pins>; - map = <&custom_maps>; - max_frame_time = <200>; - }; - - meson_irblaster: irblaster@14c { - compatible = "amlogic, meson_irblaster"; - reg = <0x14c 0x10>, - <0x40 0x4>; - interrupts = <0 198 1>; - status = "disabled"; - }; - - i2c_AO: i2c@5000 { - compatible = "amlogic,meson-i2c"; - status = "disabled"; - reg = <0x05000 0x20>; - interrupts = , - ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - clock-frequency = <100000>; - }; - - i2c_AO_slave:i2c_slave@6000 { - compatible = "amlogic, meson-i2c-slave"; - status = "disabled"; - reg = <0x6000 0x20>; - interrupts = ; - pinctrl-names="default"; - pinctrl-0=<&i2c_ao_slave_pins>; - }; - };/* end of aobus */ - - ion_dev { - compatible = "amlogic, ion_dev"; - status = "okay"; - memory-region = <&ion_cma_reserved>; - };/* end of ion_dev*/ - }; /* end of soc*/ - - custom_maps: custom_maps { - mapnum = <3>; - map0 = <&map_0>; - map1 = <&map_1>; - map2 = <&map_2>; - map_0: map_0{ - mapname = "amlogic-remote-1"; - customcode = <0xfb04>; - release_delay = <80>; - size = <44>; /*keymap size*/ - keymap = ; - }; - - map_1: map_1{ - mapname = "amlogic-remote-2"; - customcode = <0xfe01>; - release_delay = <80>; - size = <53>; - keymap = ; - }; - - map_2: map_2{ - mapname = "amlogic-remote-3"; - customcode = <0xbd02>; - release_delay = <80>; - size = <17>; - keymap = ; - }; - }; - - uart_A: serial@ffd24000 { - compatible = "amlogic, meson-uart"; - reg = <0xffd24000 0x18>; - interrupts = <0 26 1>; - status = "disabled"; - clocks = <&xtal - &clkc CLKID_UART0>; - clock-names = "clk_uart", - "clk_gate"; - fifosize = < 128 >; - pinctrl-names = "default"; - pinctrl-0 = <&a_uart_pins>; - }; - - uart_B: serial@ffd23000 { - compatible = "amlogic, meson-uart"; - reg = <0xffd23000 0x18>; - interrupts = <0 75 1>; - status = "disabled"; - clocks = <&xtal - &clkc CLKID_UART1>; - clock-names = "clk_uart", - "clk_gate"; - fifosize = < 64 >; - pinctrl-names = "default"; - pinctrl-0 = <&b_uart_pins>; - }; - - uart_C: serial@ffd22000 { - compatible = "amlogic, meson-uart"; - reg = <0xffd22000 0x18>; - interrupts = <0 93 1>; - status = "disabled"; - clocks = <&xtal - &clkc CLKID_UART1>; - clock-names = "clk_uart", - "clk_gate"; - fifosize = < 64 >; - pinctrl-names = "default"; - pinctrl-0 = <&c_uart_pins>; - }; - - sd_emmc_c: emmc@ffe07000 { - status = "okay"; - compatible = "amlogic, meson-mmc-tl1"; - reg = <0xffe07000 0x800>; - interrupts = <0 191 1>; - pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; - pinctrl-0 = <&emmc_clk_cmd_pins>; - pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_P0_COMP>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_FCLK_DIV5>, - <&xtal>; - clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; - - bus-width = <8>; - cap-sd-highspeed; - cap-mmc-highspeed; - /* mmc-ddr-1_8v; */ - /* mmc-hs200-1_8v; */ - - max-frequency = <200000000>; - non-removable; - disable-wp; - emmc { - pinname = "emmc"; - ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ - /*caps defined in dts*/ - tx_delay = <0>; - max_req_size = <0x20000>; /**128KB*/ - gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; - hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; - card_type = <1>; - /* 1:mmc card(include eMMC), - * 2:sd card(include tSD) - */ - }; - }; - - sd_emmc_b: sd@ffe05000 { - status = "okay"; - compatible = "amlogic, meson-mmc-tl1"; - reg = <0xffe05000 0x800>; - interrupts = <0 190 1>; - - pinctrl-names = "sd_all_pins", - "sd_clk_cmd_pins", - "sd_1bit_pins", - "sd_clk_cmd_uart_pins", - "sd_1bit_uart_pins", - "sd_to_ao_uart_pins", - "ao_to_sd_uart_pins", - "sd_to_ao_jtag_pins", - "ao_to_sd_jtag_pins"; - pinctrl-0 = <&sd_all_pins>; - pinctrl-1 = <&sd_clk_cmd_pins>; - pinctrl-2 = <&sd_1bit_pins>; - pinctrl-3 = <&sd_to_ao_uart_clr_pins - &sd_clk_cmd_pins &ao_to_sd_uart_pins>; - pinctrl-4 = <&sd_to_ao_uart_clr_pins - &sd_1bit_pins &ao_to_sd_uart_pins>; - pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; - pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; - pinctrl-7 = <&sd_all_pins &sd_to_ao_uart_pins>; - pinctrl-8 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; - - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_P0_COMP>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_FCLK_DIV5>, - <&xtal>; - clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; - - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <100000000>; - disable-wp; - sd { - pinname = "sd"; - ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ - max_req_size = <0x20000>; /**128KB*/ - gpio_dat3 = <&gpio GPIOC_3 GPIO_ACTIVE_HIGH>; - jtag_pin = <&gpio GPIOC_0 GPIO_ACTIVE_HIGH>; - gpio_cd = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; - card_type = <5>; - /* 3:sdio device(ie:sdio-wifi), - * 4:SD combo (IO+mem) card - */ - }; - }; - - spifc: spifc@ffd14000 { - compatible = "amlogic,aml-spi-nor"; - status = "disabled"; - - reg = <0xffd14000 0x80>; - pinctrl-names = "default"; - pinctrl-0 = <&spifc_all_pins>; - clock-names = "core"; - clocks = <&clkc CLKID_CLK81>; - - spi-nor@0 { - compatible = "jedec,spi-nor"; - spifc-frequency = <40000000>; - read-capability = <4>;/* dual read 1_1_2 */ - spifc-io-width = <4>; - }; - }; - - slc_nand: nand-controller@0xFFE07800 { - compatible = "amlogic, aml_mtd_nand"; - status = "disabled"; - reg = <0xFFE07800 0x200>; - interrupts = <0 34 1>; - - pinctrl-names = "nand_rb_mod", "nand_norb_mod", "nand_cs_only"; - pinctrl-0 = <&all_nand_pins>; - pinctrl-1 = <&all_nand_pins>; - pinctrl-2 = <&nand_cs_pins>; - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_P0_COMP>; - clock-names = "core", "clkin"; - - device_id = <0>; - /*fip/tpl configurations, must be same - *with uboot if bl_mode was set as 1 - *bl_mode: 0 compact mode;1 descrete mode - *if bl_mode was set as 1,fip configuration will work - */ - bl_mode = <1>; - /*copy count of fip*/ - fip_copies = <4>; - /*size of each fip copy*/ - fip_size = <0x200000>; - nand_clk_ctrl = <0xFFE07000>; - /*partions defined in dts*/ - }; - - mesonstream { - compatible = "amlogic, codec, streambuf"; - status = "okay"; - clocks = <&clkc CLKID_U_PARSER - &clkc CLKID_DEMUX - &clkc CLKID_AHB_ARB0 - &clkc CLKID_DOS - &clkc CLKID_VDEC_MUX - &clkc CLKID_HCODEC_MUX - &clkc CLKID_HEVC_MUX - &clkc CLKID_HEVCF_MUX>; - clock-names = "parser_top", - "demux", - "ahbarb0", - "vdec", - "clk_vdec_mux", - "clk_hcodec_mux", - "clk_hevc_mux", - "clk_hevcb_mux"; - }; - - vcodec-dec { - compatible = "amlogic, vcodec-dec"; - status = "okay"; - }; - - vdec { - compatible = "amlogic, vdec"; - status = "okay"; - interrupts = <0 3 1 - 0 23 1 - 0 32 1 - 0 43 1 - 0 44 1 - 0 45 1>; - interrupt-names = "vsync", - "demux", - "parser", - "mailbox_0", - "mailbox_1", - "mailbox_2"; - }; - - canvas: canvas { - compatible = "amlogic, meson, canvas"; - status = "okay"; - reg = <0xff638000 0x2000>; - }; - - codec_io: codec_io { - compatible = "amlogic, codec_io"; - status = "okay"; - #address-cells=<1>; - #size-cells=<1>; - ranges; - io_cbus_base{ - reg = <0xffd00000 0x100000>; - }; - io_dos_base{ - reg = <0xff620000 0x10000>; - }; - io_hiubus_base{ - reg = <0xff63c000 0x2000>; - }; - io_aobus_base{ - reg = <0xff800000 0x10000>; - }; - io_vcbus_base{ - reg = <0xff900000 0x40000>; - }; - io_dmc_base{ - reg = <0xff638000 0x2000>; - }; - io_efuse_base{ - reg = <0xff630000 0x2000>; - }; - }; - - rdma { - compatible = "amlogic, meson-tl1, rdma"; - status = "okay"; - interrupts = <0 89 1>; - interrupt-names = "rdma"; - }; - - meson_fb: fb { - compatible = "amlogic, meson-tl1"; - memory-region = <&logo_reserved>; - status = "disabled"; - interrupts = <0 3 1 - 0 56 1 - 0 89 1>; - interrupt-names = "viu-vsync", "viu2-vsync", "rdma"; - /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ - display_mode_default = "1080p60hz"; - scale_mode = <1>; - /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ - display_size_default = <1920 1080 1920 2160 32>; - /*1920*1080*4*3 = 0x17BB000*/ - clocks = <&clkc CLKID_VPU_CLKC_MUX>; - clock-names = "vpu_clkc"; - }; - - ge2d { - compatible = "amlogic, ge2d-g12a"; - status = "okay"; - interrupts = <0 146 1>; - interrupt-names = "ge2d"; - clocks = <&clkc CLKID_VAPB_MUX>, - <&clkc CLKID_G2D>, - <&clkc CLKID_GE2D_GATE>; - clock-names = "clk_vapb_0", - "clk_ge2d", - "clk_ge2d_gate"; - reg = <0xff940000 0x10000>; - }; - - meson-amvideom { - compatible = "amlogic, amvideom"; - status = "okay"; - interrupts = <0 3 1>; - interrupt-names = "vsync"; - }; - - ionvideo { - compatible = "amlogic, ionvideo"; - status = "okay"; - }; - - amlvideo { - compatible = "amlogic, amlvideo"; - status = "okay"; - }; - - vdac { - compatible = "amlogic, vdac-tl1"; - status = "okay"; - }; - - dmc_monitor { - compatible = "amlogic, dmc_monitor"; - status = "okay"; - reg_base = <0xff638800>; - interrupts = ; - }; - - efuse: efuse{ - compatible = "amlogic, efuse"; - read_cmd = <0x82000030>; - write_cmd = <0x82000031>; - get_max_cmd = <0x82000033>; - key = <&efusekey>; - clocks = <&clkc CLKID_EFUSE>; - clock-names = "efuse_clk"; - status = "disabled"; - }; - - efusekey:efusekey{ - keynum = <4>; - key0 = <&key_0>; - key1 = <&key_1>; - key2 = <&key_2>; - key3 = <&key_3>; - key_0:key_0{ - keyname = "mac"; - offset = <0>; - size = <6>; - }; - key_1:key_1{ - keyname = "mac_bt"; - offset = <6>; - size = <6>; - }; - key_2:key_2{ - keyname = "mac_wifi"; - offset = <12>; - size = <6>; - }; - key_3:key_3{ - keyname = "usid"; - offset = <18>; - size = <16>; - }; - }; -}; /* end of / */ - -&pinctrl_aobus { - sd_to_ao_uart_clr_pins: sd_to_ao_uart_clr_pins { - mux { - groups = "GPIOAO_0", - "GPIOAO_1", - "GPIOAO_2", - "GPIOAO_3", - "GPIOAO_4", - "GPIOAO_5", - "GPIOAO_6", - "GPIOAO_7", - "GPIOAO_8", - "GPIOAO_9", - "GPIOAO_10", - "GPIOAO_11", - "GPIOE_0", - "GPIOE_1", - "GPIOE_2", - "GPIO_TEST_N"; - function = "gpio_aobus"; - }; - }; - - sd_to_ao_uart_pins: sd_to_ao_uart_pins { - mux { - groups = "uart_ao_a_tx", - "uart_ao_a_rx", - "uart_ao_a_cts", - "uart_ao_a_rts"; - function = "uart_ao_a"; - bias-pull-up; - input-enable; - }; - }; - - remote_pins:remote_pin { - mux { - groups = "remote_input_ao"; - function = "remote_input_ao"; - }; - }; - - pwm_ao_a_pins: pwm_ao_a { - mux { - groups = "pwm_ao_a"; - function = "pwm_ao_a"; - }; - }; - - pwm_ao_a_hiz_pins: pwm_ao_a_hiz { - mux { - groups = "pwm_ao_a_hiz"; - function = "pwm_ao_a"; - }; - }; - - pwm_ao_b_pins: pwm_ao_b { - mux { - groups = "pwm_ao_b"; - function = "pwm_ao_b"; - }; - }; - - pwm_ao_c_pins1: pwm_ao_c_pins1 { - mux { - groups = "pwm_ao_c_4"; - function = "pwm_ao_c"; - }; - }; - - pwm_ao_c_pins2: pwm_ao_c_pins2 { - mux { - groups = "pwm_ao_c_6"; - function = "pwm_ao_c"; - }; - }; - - pwm_ao_c_hiz_pins1: pwm_ao_c_hiz1 { - mux { - groups = "pwm_ao_c_hiz_4"; - function = "pwm_ao_c"; - }; - }; - - pwm_ao_c_hiz_pins2: pwm_ao_c_hiz2 { - mux { - groups = "pwm_ao_c_hiz_7"; - function = "pwm_ao_c"; - }; - }; - - pwm_ao_d_pins1: pwm_ao_d_pins1 { - mux { - groups = "pwm_ao_d_5"; - function = "pwm_ao_d"; - }; - }; - - pwm_ao_d_pins2: pwm_ao_d_pins2 { - mux { - groups = "pwm_ao_d_10"; - function = "pwm_ao_d"; - }; - }; - - pwm_ao_d_pins3: pwm_ao_d_pins3 { - mux { - groups = "pwm_ao_d_e"; - function = "pwm_ao_d"; - }; - }; - - pwm_a_e2: pwm_a_e2 { - mux { - groups = "pwm_a_e2"; - function = "pwm_a_e2"; - }; - }; - - i2c_ao_2_pins:i2c_ao_2 { - mux { - groups = "i2c_ao_sck_2", - "i2c_ao_sda_3"; - function = "i2c_ao"; - bias-pull-up; - drive-strength = <3>; - }; - }; - - i2c_ao_e_pins:i2c_ao_e { - mux { - groups = "i2c_ao_sck_e", - "i2c_ao_sda_e"; - function = "i2c_ao"; - bias-pull-up; - drive-strength = <3>; - }; - }; - - i2c_ao_slave_pins:i2c_ao_slave { - mux { - groups = "i2c_ao_slave_sck", - "i2c_ao_slave_sda"; - function = "i2c_ao_slave"; - }; - }; - - ao_uart_pins:ao_uart { - mux { - groups = "uart_ao_a_rx", - "uart_ao_a_tx"; - function = "uart_ao_a"; - }; - }; - - ao_b_uart_pins1:ao_b_uart1 { - mux { - groups = "uart_ao_b_tx_2", - "uart_ao_b_rx_3"; - function = "uart_ao_b"; - }; - }; - - ao_b_uart_pins2:ao_b_uart2 { - mux { - groups = "uart_ao_b_tx_8", - "uart_ao_b_rx_9"; - function = "uart_ao_b"; - }; - }; - - irblaster_pins:irblaster_pin { - mux { - groups = "remote_out_ao"; - function = "remote_out_ao"; - }; - }; - - irblaster_pins1:irblaster_pin1 { - mux { - groups = "remote_out_ao9"; - function = "remote_out_ao"; - }; - }; -}; - -&pinctrl_periphs { - /* sdemmc portC */ - emmc_clk_cmd_pins: emmc_clk_cmd_pins { - mux { - groups = "emmc_clk", - "emmc_cmd"; - function = "emmc"; - input-enable; - bias-pull-up; - drive-strength = <3>; - }; - }; - - emmc_conf_pull_up: emmc_conf_pull_up { - mux { - groups = "emmc_nand_d7", - "emmc_nand_d6", - "emmc_nand_d5", - "emmc_nand_d4", - "emmc_nand_d3", - "emmc_nand_d2", - "emmc_nand_d1", - "emmc_nand_d0", - "emmc_clk", - "emmc_cmd"; - function = "emmc"; - input-enable; - bias-pull-up; - drive-strength = <3>; - }; - }; - - emmc_conf_pull_done: emmc_conf_pull_done { - mux { - groups = "emmc_nand_ds"; - function = "emmc"; - input-enable; - bias-pull-down; - drive-strength = <3>; - }; - }; - - /* sdemmc portB */ - sd_clk_cmd_pins: sd_clk_cmd_pins { - mux { - groups = "sdcard_cmd", - "sdcard_clk"; - function = "sdcard"; - input-enable; - bias-pull-up; - drive-strength = <3>; - }; - }; - - sd_all_pins: sd_all_pins { - mux { - groups = "sdcard_d0", - "sdcard_d1", - "sdcard_d2", - "sdcard_d3", - "sdcard_cmd", - "sdcard_clk"; - function = "sdcard"; - input-enable; - bias-pull-up; - drive-strength = <3>; - }; - }; - - sd_1bit_pins: sd_1bit_pins { - mux { - groups = "sdcard_d0", - "sdcard_cmd", - "sdcard_clk"; - function = "sdcard"; - input-enable; - bias-pull-up; - drive-strength = <3>; - }; - }; - - ao_to_sd_uart_pins: ao_to_sd_uart_pins { - mux { - groups = "uart_ao_a_rx_c", - "uart_ao_a_tx_c", - "uart_ao_a_rx_w3", - "uart_ao_a_tx_w2", - "uart_ao_a_rx_w7", - "uart_ao_a_tx_w6", - "uart_ao_a_rx_w11", - "uart_ao_a_tx_w10"; - function = "uart_ao_a_ee"; - bias-pull-up; - input-enable; - }; - }; - - all_nand_pins: all_nand_pins { - mux { - groups = "emmc_nand_d0", - "emmc_nand_d1", - "emmc_nand_d2", - "emmc_nand_d3", - "emmc_nand_d4", - "emmc_nand_d5", - "emmc_nand_d6", - "emmc_nand_d7", - "nand_ce0", - "nand_ale", - "nand_cle", - "nand_wen_clk", - "nand_ren_wr"; - function = "nand"; - input-enable; - drive-strength = <3>; - }; - }; - - nand_cs_pins:nand_cs { - mux { - groups = "nand_ce0"; - function = "nand"; - drive-strength = <3>; - }; - }; - - /* sdemmc portA */ - sdio_clk_cmd_pins: sdio_clk_cmd_pins { - mux { - groups = "sdio_clk", - "sdio_cmd"; - function = "sdio"; - input-enable; - bias-pull-up; - drive-strength = <3>; - }; - }; - - sdio_all_pins: sdio_all_pins { - mux { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_clk", - "sdio_cmd"; - function = "sdio"; - input-enable; - bias-pull-up; - drive-strength = <3>; - }; - }; - - spifc_cs_pin:spifc_cs_pin { - mux { - groups = "nor_cs"; - function = "nor"; - bias-pull-up; - }; - }; - - spifc_pulldown: spifc_pulldown { - mux { - groups = "nor_d", - "nor_q", - "nor_c"; - function = "nor"; - bias-pull-down; - }; - }; - - spifc_pullup: spifc_pullup { - mux { - groups = "nor_cs"; - function = "nor"; - bias-pull-up; - }; - }; - - spifc_all_pins: spifc_all_pins { - mux { - groups = "nor_d", - "nor_q", - "nor_c", - "nor_hold", - "nor_wp"; - function = "nor"; - input-enable; - bias-pull-down; - }; - }; - - pwm_a_pins: pwm_a { - mux { - groups = "pwm_a"; - function = "pwm_a"; - }; - }; - - pwm_b_pins1: pwm_b_pins1 { - mux { - groups = "pwm_b_c"; - function = "pwm_b"; - }; - }; - - pwm_b_pins2: pwm_b_pins2 { - mux { - groups = "pwm_b_z"; - function = "pwm_b"; - }; - }; - - pwm_c_pins1: pwm_c_pins1 { - mux { - groups = "pwm_c_dv"; - function = "pwm_c"; - }; - }; - - pwm_c_pins2: pwm_c_pins2 { - mux { - groups = "pwm_c_h"; - function = "pwm_c"; - }; - }; - - pwm_c_pins3: pwm_c_pins3 { - mux { - groups = "pwm_c_z"; - function = "pwm_c"; - }; - }; - - pwm_d_pins1: pwm_d_pins1 { - mux { - groups = "pwm_d_dv"; - function = "pwm_d"; - }; - }; - - pwm_d_pins2: pwm_d_pins2 { - mux { - groups = "pwm_d_z"; - function = "pwm_d"; - }; - }; - - pwm_e_pins1: pwm_e1 { - mux { - groups = "pwm_e_dv"; - function = "pwm_e"; - }; - }; - - pwm_e_pins2: pwm_e2 { - mux { - groups = "pwm_e_z"; - function = "pwm_e"; - }; - }; - - pwm_f_pins1: pwm_f_pins1 { - mux { - groups = "pwm_f_dv"; - function = "pwm_f"; - }; - }; - - pwm_f_pins2: pwm_f_pins2 { - mux { - groups = "pwm_f_z"; - function = "pwm_f"; - }; - }; - - i2c0_c_pins:i2c0_c { - mux { - groups = "i2c0_sda_c", - "i2c0_sck_c"; - function = "i2c0"; - bias-pull-up; - drive-strength = <3>; - }; - }; - - i2c0_dv_pins:i2c0_dv { - mux { - groups = "i2c0_sda_dv", - "i2c0_sck_dv"; - function = "i2c0"; - bias-pull-up; - drive-strength = <3>; - }; - }; - - i2c1_z_pins:i2c1_z { - mux { - groups = "i2c1_sda_z", - "i2c1_sck_z"; - function = "i2c1"; - bias-pull-up; - drive-strength = <3>; - }; - }; - - i2c1_h_pins:i2c1_h { - mux { - groups = "i2c1_sda_h", - "i2c1_sck_h"; - function = "i2c1"; - bias-pull-up; - drive-strength = <3>; - }; - }; - - i2c2_h_pins:i2c2_h { - mux { - groups = "i2c2_sda_h", - "i2c2_sck_h"; - function = "i2c2"; - bias-pull-up; - drive-strength = <3>; - }; - }; - - i2c2_z_pins:i2c2_z { - mux { - groups = "i2c2_sda_z", - "i2c2_sck_z"; - function = "i2c2"; - bias-pull-up; - drive-strength = <3>; - }; - }; - - i2c3_h1_pins:i2c3_h1 { - mux { - groups = "i2c3_sda_h1", - "i2c3_sck_h0"; - function = "i2c3"; - bias-pull-up; - drive-strength = <3>; - }; - }; - - i2c3_h20_pins:i2c3_h3 { - mux { - groups = "i2c3_sda_h20", - "i2c3_sck_h19"; - function = "i2c3"; - bias-pull-up; - drive-strength = <3>; - }; - }; - - i2c3_dv_pins:i2c3_dv { - mux { - groups = "i2c3_sda_dv", - "i2c3_sck_dv"; - function = "i2c3"; - bias-pull-up; - drive-strength = <3>; - }; - }; - - i2c3_c_pins:i2c3_c { - mux { - groups = "i2c3_sda_c", - "i2c3_sck_c"; - function = "i2c3"; - bias-pull-up; - drive-strength = <3>; - }; - }; - - spicc0_pins_h: spicc0_pins_h { - mux { - groups = "spi0_mosi_h", - "spi0_miso_h", - "spi0_clk_h"; - function = "spi0"; - drive-strength = <1>; - }; - }; - - spicc1_pins_dv: spicc1_pins_dv { - mux { - groups = "spi1_mosi_dv", - "spi1_miso_dv", - "spi1_clk_dv"; - function = "spi1"; - drive-strength = <1>; - }; - }; - - internal_eth_pins: internal_eth_pins { - mux { - groups = "eth_link_led", - "eth_act_led"; - function = "eth"; - }; - }; - - internal_gpio_pins: internal_gpio_pins { - mux { - groups = "GPIOZ_14", - "GPIOZ_15"; - function = "gpio_periphs"; - bias-disable; - input-enable; - }; - }; - - external_eth_pins: external_eth_pins { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_rgmii_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_rxd2_rgmii", - "eth_rxd3_rgmii", - "eth_rgmii_tx_clk", - "eth_txen", - "eth_txd0", - "eth_txd1", - "eth_txd2_rgmii", - "eth_txd3_rgmii"; - function = "eth"; - drive-strength = <3>; - }; - }; - - a_uart_pins:a_uart { - mux { - groups = "uart_a_tx", - "uart_a_rx", - "uart_a_cts", - "uart_a_rts"; - function = "uart_a"; - }; - }; - - b_uart_pins:b_uart { - mux { - groups = "uart_b_tx", - "uart_b_rx"; - function = "uart_b"; - }; - }; - - c_uart_pins:c_uart { - mux { - groups = "uart_c_tx", - "uart_c_rx"; - function = "uart_c"; - }; - }; - -}; diff --git a/include/dt-bindings/clock/amlogic,tm2-audio-clk.h b/include/dt-bindings/clock/amlogic,tm2-audio-clk.h new file mode 100644 index 000000000000..a70cf1ef636b --- /dev/null +++ b/include/dt-bindings/clock/amlogic,tm2-audio-clk.h @@ -0,0 +1,97 @@ +/* + * include/dt-bindings/clock/amlogic,tm2-audio-clk.h + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __TM2_AUDIO_CLK_H__ +#define __TM2_AUDIO_CLK_H__ + +/* + * CLKID audio index values + */ + +#define CLKID_AUDIO_GATE_DDR_ARB 0 +#define CLKID_AUDIO_GATE_PDM 1 +#define CLKID_AUDIO_GATE_TDMINA 2 +#define CLKID_AUDIO_GATE_TDMINB 3 +#define CLKID_AUDIO_GATE_TDMINC 4 +#define CLKID_AUDIO_GATE_TDMINLB 5 +#define CLKID_AUDIO_GATE_TDMOUTA 6 +#define CLKID_AUDIO_GATE_TDMOUTB 7 +#define CLKID_AUDIO_GATE_TDMOUTC 8 +#define CLKID_AUDIO_GATE_FRDDRA 9 +#define CLKID_AUDIO_GATE_FRDDRB 10 +#define CLKID_AUDIO_GATE_FRDDRC 11 +#define CLKID_AUDIO_GATE_TODDRA 12 +#define CLKID_AUDIO_GATE_TODDRB 13 +#define CLKID_AUDIO_GATE_TODDRC 14 +#define CLKID_AUDIO_GATE_LOOPBACKA 15 +#define CLKID_AUDIO_GATE_SPDIFIN 16 +#define CLKID_AUDIO_GATE_SPDIFOUT_A 17 +#define CLKID_AUDIO_GATE_RESAMPLEA 18 +#define CLKID_AUDIO_GATE_RESERVED0 19 +#define CLKID_AUDIO_GATE_RESERVED1 20 +#define CLKID_AUDIO_GATE_SPDIFOUT_B 21 +#define CLKID_AUDIO_GATE_EQDRC 22 +#define CLKID_AUDIO_GATE_RESERVED2 23 +#define CLKID_AUDIO_GATE_RESERVED3 24 +#define CLKID_AUDIO_GATE_RESERVED4 25 +#define CLKID_AUDIO_GATE_RESAMPLEB 26 +#define CLKID_AUDIO_GATE_TOVAD 27 +#define CLKID_AUDIO_GATE_AUDIOLOCKER 28 +#define CLKID_AUDIO_GATE_SPDIFIN_LB 29 +#define CLKID_AUDIO_GATE_FRATV 30 +#define CLKID_AUDIO_GATE_FRHDMIRX 31 + +/* Gate En1 */ +#define CLKID_AUDIO_GATE_FRDDRD 32 +#define CLKID_AUDIO_GATE_TODDRD 33 +#define CLKID_AUDIO_GATE_LOOPBACKB 34 +#define CLKID_AUDIO_GATE_FRDDRE 35 +#define CLKID_AUDIO_GATE_TODDRE 36 +#define CLKID_AUDIO_GATE_EARCTX 37 +#define CLKID_AUDIO_GATE_EARCRX 38 +#define CLKID_AUDIO_GATE_RESAMPLEB_OLD 39 +#define CLKID_AUDIO_GATE_LOCKER 40 + +#define CLKID_AUDIO_GATE_MAX 41 + +#define MCLK_BASE CLKID_AUDIO_GATE_MAX +#define CLKID_AUDIO_MCLK_A (MCLK_BASE + 0) +#define CLKID_AUDIO_MCLK_B (MCLK_BASE + 1) +#define CLKID_AUDIO_MCLK_C (MCLK_BASE + 2) +#define CLKID_AUDIO_MCLK_D (MCLK_BASE + 3) +#define CLKID_AUDIO_MCLK_E (MCLK_BASE + 4) +#define CLKID_AUDIO_MCLK_F (MCLK_BASE + 5) + +#define CLKID_AUDIO_SPDIFIN (MCLK_BASE + 6) +#define CLKID_AUDIO_SPDIFOUT_A (MCLK_BASE + 7) +#define CLKID_AUDIO_RESAMPLE_A (MCLK_BASE + 8) +#define CLKID_AUDIO_LOCKER_OUT (MCLK_BASE + 9) +#define CLKID_AUDIO_LOCKER_IN (MCLK_BASE + 10) +#define CLKID_AUDIO_PDMIN0 (MCLK_BASE + 11) +#define CLKID_AUDIO_PDMIN1 (MCLK_BASE + 12) +#define CLKID_AUDIO_SPDIFOUT_B (MCLK_BASE + 13) +#define CLKID_AUDIO_RESAMPLE_B (MCLK_BASE + 14) +#define CLKID_AUDIO_SPDIFIN_LB (MCLK_BASE + 15) +#define CLKID_AUDIO_EQDRC (MCLK_BASE + 16) +#define CLKID_AUDIO_VAD (MCLK_BASE + 17) +#define CLKID_EARCTX_CMDC (MCLK_BASE + 18) +#define CLKID_EARCTX_DMAC (MCLK_BASE + 19) +#define CLKID_EARCRX_CMDC (MCLK_BASE + 20) +#define CLKID_EARCRX_DMAC (MCLK_BASE + 21) + +#define NUM_AUDIO_CLKS (MCLK_BASE + 22) +#endif /* __TM2_AUDIO_CLK_H__ */ diff --git a/sound/soc/amlogic/auge/Makefile b/sound/soc/amlogic/auge/Makefile index 91825bf36d6c..b8d6cc8eb8e8 100644 --- a/sound/soc/amlogic/auge/Makefile +++ b/sound/soc/amlogic/auge/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_AMLOGIC_SND_SOC_AUGE) += audio_controller.o \ g12a,clocks.o \ tl1,clocks.o \ sm1,clocks.o \ + tm2,clocks.o \ card.o \ card_utils.o \ tdm.o \ diff --git a/sound/soc/amlogic/auge/audio_clks.c b/sound/soc/amlogic/auge/audio_clks.c index e02f2a562b07..4aa82c362867 100644 --- a/sound/soc/amlogic/auge/audio_clks.c +++ b/sound/soc/amlogic/auge/audio_clks.c @@ -40,6 +40,10 @@ static const struct of_device_id audio_clocks_of_match[] = { .compatible = "amlogic, sm1-audio-clocks", .data = &sm1_audio_clks_init, }, + { + .compatible = "amlogic, tm2-audio-clocks", + .data = &tm2_audio_clks_init, + }, {}, }; MODULE_DEVICE_TABLE(of, audio_clocks_of_match); diff --git a/sound/soc/amlogic/auge/audio_clks.h b/sound/soc/amlogic/auge/audio_clks.h index 56a0a67b1d31..ede4ec982ced 100644 --- a/sound/soc/amlogic/auge/audio_clks.h +++ b/sound/soc/amlogic/auge/audio_clks.h @@ -94,6 +94,7 @@ extern struct audio_clk_init axg_audio_clks_init; extern struct audio_clk_init g12a_audio_clks_init; extern struct audio_clk_init tl1_audio_clks_init; extern struct audio_clk_init sm1_audio_clks_init; +extern struct audio_clk_init tm2_audio_clks_init; struct clk_chipinfo { /* force clock source as oscin(24M) */ diff --git a/sound/soc/amlogic/auge/audio_controller.c b/sound/soc/amlogic/auge/audio_controller.c index 1b50eacb3ff0..04845c530853 100644 --- a/sound/soc/amlogic/auge/audio_controller.c +++ b/sound/soc/amlogic/auge/audio_controller.c @@ -104,6 +104,7 @@ static int register_audio_controller(struct platform_device *pdev, /* gate on all clks on bringup stage, need gate separately */ aml_audiobus_write(actrl, EE_AUDIO_CLK_GATE_EN0, 0xffffffff); + aml_audiobus_write(actrl, EE_AUDIO_CLK_GATE_EN1, 0xffffffff); return 0; } diff --git a/sound/soc/amlogic/auge/card.c b/sound/soc/amlogic/auge/card.c index 3e7c82cd0ca2..4550fbca4fbf 100644 --- a/sound/soc/amlogic/auge/card.c +++ b/sound/soc/amlogic/auge/card.c @@ -877,6 +877,10 @@ static const struct of_device_id auge_of_match[] = { .compatible = "amlogic, tl1-sound-card", .data = &tl1_chipset_info, }, + { + .compatible = "amlogic, tm2-sound-card", + .data = &tl1_chipset_info, + }, {}, }; MODULE_DEVICE_TABLE(of, auge_of_match); @@ -919,9 +923,8 @@ static int aml_card_probe(struct platform_device *pdev) ret = aml_card_parse_of(np, priv); if (ret < 0) { - if (ret != -EPROBE_DEFER) - dev_err(dev, "%s, parse error %d\n", - __func__, ret); + dev_err(dev, "%s, parse error %d\n", + __func__, ret); goto err; } diff --git a/sound/soc/amlogic/auge/ddr_mngr.c b/sound/soc/amlogic/auge/ddr_mngr.c index af7560a86a1b..a12a337ce159 100644 --- a/sound/soc/amlogic/auge/ddr_mngr.c +++ b/sound/soc/amlogic/auge/ddr_mngr.c @@ -406,7 +406,7 @@ void aml_toddr_set_fifos(struct toddr *to, unsigned int thresh) if (to->chipinfo && to->chipinfo->ugt) { reg = calc_toddr_address(EE_AUDIO_TODDR_A_CTRL0, reg_base); - aml_audiobus_update_bits(actrl, reg, 0x0 << 0, 0x1 << 0); + aml_audiobus_update_bits(actrl, reg, 0x1, 0x1); } } @@ -1317,8 +1317,8 @@ void aml_frddr_set_fifos(struct frddr *fr, (depth - 1)<<24 | (thresh - 1)<<16 | 2<<8); if (fr->chipinfo && fr->chipinfo->ugt) { - reg = calc_toddr_address(EE_AUDIO_FRDDR_A_CTRL0, reg_base); - aml_audiobus_update_bits(actrl, reg, 0x0 << 0, 0x1 << 0); + reg = calc_frddr_address(EE_AUDIO_FRDDR_A_CTRL0, reg_base); + aml_audiobus_update_bits(actrl, reg, 0x1, 0x1); } } diff --git a/sound/soc/amlogic/auge/earc.c b/sound/soc/amlogic/auge/earc.c index 355e7db3a8b3..30b5f30d0aec 100644 --- a/sound/soc/amlogic/auge/earc.c +++ b/sound/soc/amlogic/auge/earc.c @@ -625,6 +625,9 @@ static const struct of_device_id earc_device_id[] = { { .compatible = "amlogic, sm1-snd-earc", }, + { + .compatible = "amlogic, tm2-snd-earc", + }, {}, }; @@ -664,7 +667,7 @@ static int earc_platform_probe(struct platform_device *pdev) if (IS_ERR(p_earc->clk_rx_gate)) { dev_err(&pdev->dev, "Can't get earc gate\n"); - return PTR_ERR(p_earc->clk_rx_gate); + /*return PTR_ERR(p_earc->clk_rx_gate);*/ } /* RX */ p_earc->clk_rx_cmdc = devm_clk_get(&pdev->dev, "rx_cmdc"); diff --git a/sound/soc/amlogic/auge/pdm_match_table.c b/sound/soc/amlogic/auge/pdm_match_table.c index 850b5093f990..27ce1dd6b5e5 100644 --- a/sound/soc/amlogic/auge/pdm_match_table.c +++ b/sound/soc/amlogic/auge/pdm_match_table.c @@ -31,6 +31,12 @@ static struct pdm_chipinfo sm1_pdm_chipinfo = { .train = true, }; +static struct pdm_chipinfo tm2_pdm_chipinfo = { + .mute_fn = true, + .truncate_data = false, + .train = true, +}; + static const struct of_device_id aml_pdm_device_id[] = { { .compatible = "amlogic, axg-snd-pdm", @@ -47,6 +53,10 @@ static const struct of_device_id aml_pdm_device_id[] = { .compatible = "amlogic, sm1-snd-pdm", .data = &sm1_pdm_chipinfo, }, + { + .compatible = "amlogic, tm2-snd-pdm", + .data = &tm2_pdm_chipinfo, + }, {} }; diff --git a/sound/soc/amlogic/auge/spdif_match_table.c b/sound/soc/amlogic/auge/spdif_match_table.c index 025301585292..c88929e55561 100644 --- a/sound/soc/amlogic/auge/spdif_match_table.c +++ b/sound/soc/amlogic/auge/spdif_match_table.c @@ -92,6 +92,20 @@ struct spdif_chipinfo sm1_spdif_b_chipinfo = { .eq_drc_en = true, }; +struct spdif_chipinfo tm2_spdif_a_chipinfo = { + .id = SPDIF_A, + .chnum_en = true, + .hold_start = true, + .eq_drc_en = true, +}; + +struct spdif_chipinfo tm2_spdif_b_chipinfo = { + .id = SPDIF_B, + .chnum_en = true, + .hold_start = true, + .eq_drc_en = true, +}; + static const struct of_device_id aml_spdif_device_id[] = { { .compatible = "amlogic, axg-snd-spdif", @@ -121,6 +135,14 @@ static const struct of_device_id aml_spdif_device_id[] = { .compatible = "amlogic, sm1-snd-spdif-b", .data = &sm1_spdif_b_chipinfo, }, + { + .compatible = "amlogic, tm2-snd-spdif-a", + .data = &tm2_spdif_a_chipinfo, + }, + { + .compatible = "amlogic, tm2-snd-spdif-b", + .data = &tm2_spdif_b_chipinfo, + }, {}, }; MODULE_DEVICE_TABLE(of, aml_spdif_device_id); diff --git a/sound/soc/amlogic/auge/tdm_match_table.c b/sound/soc/amlogic/auge/tdm_match_table.c index fd56921b4f45..38534778ae3a 100644 --- a/sound/soc/amlogic/auge/tdm_match_table.c +++ b/sound/soc/amlogic/auge/tdm_match_table.c @@ -132,6 +132,30 @@ struct tdm_chipinfo sm1_tdmc_chipinfo = { .lane_cnt = LANE_MAX1, }; +struct tdm_chipinfo tm2_tdma_chipinfo = { + .id = TDM_A, + .sclk_ws_inv = true, + .oe_fn = true, + .same_src_fn = true, + .lane_cnt = LANE_MAX0, +}; + +struct tdm_chipinfo tm2_tdmb_chipinfo = { + .id = TDM_B, + .sclk_ws_inv = true, + .oe_fn = true, + .same_src_fn = true, + .lane_cnt = LANE_MAX3, +}; + +struct tdm_chipinfo tm2_tdmc_chipinfo = { + .id = TDM_C, + .sclk_ws_inv = true, + .oe_fn = true, + .same_src_fn = true, + .lane_cnt = LANE_MAX1, +}; + static const struct of_device_id aml_tdm_device_id[] = { { .compatible = "amlogic, axg-snd-tdma", @@ -181,6 +205,18 @@ static const struct of_device_id aml_tdm_device_id[] = { .compatible = "amlogic, sm1-snd-tdmc", .data = &sm1_tdmc_chipinfo, }, + { + .compatible = "amlogic, tm2-snd-tdma", + .data = &tm2_tdma_chipinfo, + }, + { + .compatible = "amlogic, tm2-snd-tdmb", + .data = &tm2_tdmb_chipinfo, + }, + { + .compatible = "amlogic, tm2-snd-tdmc", + .data = &tm2_tdmc_chipinfo, + }, {}, }; MODULE_DEVICE_TABLE(of, aml_tdm_device_id); diff --git a/sound/soc/amlogic/auge/tm2,clocks.c b/sound/soc/amlogic/auge/tm2,clocks.c new file mode 100644 index 000000000000..aed576ec4ded --- /dev/null +++ b/sound/soc/amlogic/auge/tm2,clocks.c @@ -0,0 +1,392 @@ +/* + * sound/soc/amlogic/auge/tm2_clocks.c + * + * Copyright (C) 2019 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#undef pr_fmt +#define pr_fmt(fmt) "tm2_audio_clocks: " fmt + +#include + +#include "audio_clks.h" +#include "regs.h" + +static spinlock_t aclk_lock; + +static const char *const mclk_parent_names[] = { + "mpll0", "mpll1", "mpll2", "mpll3", "hifi_pll", + "fclk_div3", "fclk_div4", "fclk_div5"}; + +static const char *const audioclk_parent_names[] = { + "mclk_a", "mclk_b", "mclk_c", "mclk_d", "mclk_e", + "mclk_f", "i_slv_sclk_a", "i_slv_sclk_b", "i_slv_sclk_c", + "i_slv_sclk_d", "i_slv_sclk_e", "i_slv_sclk_f", "i_slv_sclk_g", + "i_slv_sclk_h", "i_slv_sclk_i", "i_slv_sclk_j"}; + +CLOCK_GATE(audio_ddr_arb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 0); +CLOCK_GATE(audio_pdm, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 1); +CLOCK_GATE(audio_tdmina, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 2); +CLOCK_GATE(audio_tdminb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 3); +CLOCK_GATE(audio_tdminc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 4); +CLOCK_GATE(audio_tdminlb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 5); +CLOCK_GATE(audio_tdmouta, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 6); +CLOCK_GATE(audio_tdmoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 7); +CLOCK_GATE(audio_tdmoutc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 8); +CLOCK_GATE(audio_frddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 9); +CLOCK_GATE(audio_frddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 10); +CLOCK_GATE(audio_frddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 11); +CLOCK_GATE(audio_toddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 12); +CLOCK_GATE(audio_toddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 13); +CLOCK_GATE(audio_toddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 14); +CLOCK_GATE(audio_loopbacka, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 15); +CLOCK_GATE(audio_spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 16); +CLOCK_GATE(audio_spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 17); +CLOCK_GATE(audio_resamplea, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 18); +CLOCK_GATE(audio_reserved0, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 19); +CLOCK_GATE(audio_reserved1, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 20); +CLOCK_GATE(audio_spdifoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 21); +CLOCK_GATE(audio_eqdrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 22); +CLOCK_GATE(audio_reserved2, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 23); +CLOCK_GATE(audio_reserved3, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 24); +CLOCK_GATE(audio_reserved4, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 25); +CLOCK_GATE(audio_resampleb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 26); +CLOCK_GATE(audio_tovad, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 27); +CLOCK_GATE(audio_audiolocker, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 28); +CLOCK_GATE(audio_spdifin_lb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 29); +CLOCK_GATE(audio_fratv, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 30); +CLOCK_GATE(audio_frhdmirx, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 31); + +CLOCK_GATE(audio_frddrd, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN1), 0); +CLOCK_GATE(audio_toddrd, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN1), 1); +CLOCK_GATE(audio_loopbackb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN1), 2); +CLOCK_GATE(audio_frddre, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN1), 3); +CLOCK_GATE(audio_toddre, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN1), 4); +CLOCK_GATE(audio_earctx, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN1), 5); +CLOCK_GATE(audio_earcrx, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN1), 6); +CLOCK_GATE(audio_resampleb_old, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN1), 7); +CLOCK_GATE(audio_locker, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN1), 8); + + +static struct clk_gate *tm2_audio_clk_gates[] = { + &audio_ddr_arb, + &audio_pdm, + &audio_tdmina, + &audio_tdminb, + &audio_tdminc, + &audio_tdminlb, + &audio_tdmouta, + &audio_tdmoutb, + &audio_tdmoutc, + &audio_frddra, + &audio_frddrb, + &audio_frddrc, + &audio_toddra, + &audio_toddrb, + &audio_toddrc, + &audio_loopbacka, + &audio_spdifin, + &audio_spdifout, + &audio_resamplea, + &audio_reserved0, + &audio_reserved1, + &audio_spdifoutb, + &audio_eqdrc, + &audio_reserved2, + &audio_reserved3, + &audio_reserved4, + &audio_resampleb, + &audio_tovad, + &audio_audiolocker, + &audio_spdifin_lb, + &audio_fratv, + &audio_frhdmirx, + + &audio_frddrd, + &audio_toddrd, + &audio_loopbackb, + &audio_frddre, + &audio_toddre, + &audio_earctx, + &audio_earcrx, + &audio_resampleb_old, + &audio_locker, +}; + +/* Array of all clocks provided by this provider */ +static struct clk_hw *tm2_audio_clk_hws[] = { + [CLKID_AUDIO_GATE_DDR_ARB] = &audio_ddr_arb.hw, + [CLKID_AUDIO_GATE_PDM] = &audio_pdm.hw, + [CLKID_AUDIO_GATE_TDMINA] = &audio_tdmina.hw, + [CLKID_AUDIO_GATE_TDMINB] = &audio_tdminb.hw, + [CLKID_AUDIO_GATE_TDMINC] = &audio_tdminc.hw, + [CLKID_AUDIO_GATE_TDMINLB] = &audio_tdminlb.hw, + [CLKID_AUDIO_GATE_TDMOUTA] = &audio_tdmouta.hw, + [CLKID_AUDIO_GATE_TDMOUTB] = &audio_tdmoutb.hw, + [CLKID_AUDIO_GATE_TDMOUTC] = &audio_tdmoutc.hw, + [CLKID_AUDIO_GATE_FRDDRA] = &audio_frddra.hw, + [CLKID_AUDIO_GATE_FRDDRB] = &audio_frddrb.hw, + [CLKID_AUDIO_GATE_FRDDRC] = &audio_frddrc.hw, + [CLKID_AUDIO_GATE_TODDRA] = &audio_toddra.hw, + [CLKID_AUDIO_GATE_TODDRB] = &audio_toddrb.hw, + [CLKID_AUDIO_GATE_TODDRC] = &audio_toddrc.hw, + [CLKID_AUDIO_GATE_LOOPBACKA] = &audio_loopbacka.hw, + [CLKID_AUDIO_GATE_SPDIFIN] = &audio_spdifin.hw, + [CLKID_AUDIO_GATE_SPDIFOUT_A] = &audio_spdifout.hw, + [CLKID_AUDIO_GATE_RESAMPLEA] = &audio_resamplea.hw, + [CLKID_AUDIO_GATE_RESERVED0] = &audio_reserved0.hw, + [CLKID_AUDIO_GATE_RESERVED1] = &audio_reserved1.hw, + [CLKID_AUDIO_GATE_SPDIFOUT_B] = &audio_spdifoutb.hw, + [CLKID_AUDIO_GATE_EQDRC] = &audio_eqdrc.hw, + [CLKID_AUDIO_GATE_RESERVED2] = &audio_reserved2.hw, + [CLKID_AUDIO_GATE_RESERVED3] = &audio_reserved3.hw, + [CLKID_AUDIO_GATE_RESERVED4] = &audio_reserved4.hw, + [CLKID_AUDIO_GATE_RESAMPLEB] = &audio_resampleb.hw, + [CLKID_AUDIO_GATE_TOVAD] = &audio_tovad.hw, + [CLKID_AUDIO_GATE_AUDIOLOCKER] = &audio_audiolocker.hw, + [CLKID_AUDIO_GATE_SPDIFIN_LB] = &audio_spdifin_lb.hw, + [CLKID_AUDIO_GATE_FRATV] = &audio_fratv.hw, + [CLKID_AUDIO_GATE_FRHDMIRX] = &audio_frhdmirx.hw, + + [CLKID_AUDIO_GATE_FRDDRD] = &audio_frddrd.hw, + [CLKID_AUDIO_GATE_TODDRD] = &audio_toddrd.hw, + [CLKID_AUDIO_GATE_LOOPBACKB] = &audio_loopbackb.hw, + [CLKID_AUDIO_GATE_FRDDRE] = &audio_frddre.hw, + [CLKID_AUDIO_GATE_TODDRE] = &audio_toddre.hw, + [CLKID_AUDIO_GATE_EARCTX] = &audio_earctx.hw, + [CLKID_AUDIO_GATE_EARCRX] = &audio_earcrx.hw, + [CLKID_AUDIO_GATE_RESAMPLEB_OLD] = &audio_resampleb_old.hw, + [CLKID_AUDIO_GATE_LOCKER] = &audio_locker.hw, +}; + +static int tm2_clk_gates_init(struct clk **clks, void __iomem *iobase) +{ + int clkid; + + if (ARRAY_SIZE(tm2_audio_clk_gates) != MCLK_BASE) { + pr_err("check clk gates number\n"); + return -EINVAL; + } + + for (clkid = 0; clkid < MCLK_BASE; clkid++) { + tm2_audio_clk_gates[clkid]->reg = iobase; + clks[clkid] = clk_register(NULL, tm2_audio_clk_hws[clkid]); + WARN_ON(IS_ERR_OR_NULL(clks[clkid])); + } + + return 0; +} + +/* mclk_a */ +CLOCK_COM_MUX(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(1)), 0x7, 24); +CLOCK_COM_DIV(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(1)), 0, 16); +CLOCK_COM_GATE(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(1)), 31); +/* mclk_b */ +CLOCK_COM_MUX(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(1)), 0x7, 24); +CLOCK_COM_DIV(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(1)), 0, 16); +CLOCK_COM_GATE(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(1)), 31); +/* mclk_c */ +CLOCK_COM_MUX(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(1)), 0x7, 24); +CLOCK_COM_DIV(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(1)), 0, 16); +CLOCK_COM_GATE(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(1)), 31); +/* mclk_d */ +CLOCK_COM_MUX(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(1)), 0x7, 24); +CLOCK_COM_DIV(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(1)), 0, 16); +CLOCK_COM_GATE(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(1)), 31); +/* mclk_e */ +CLOCK_COM_MUX(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(1)), 0x7, 24); +CLOCK_COM_DIV(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(1)), 0, 16); +CLOCK_COM_GATE(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(1)), 31); +/* mclk_f */ +CLOCK_COM_MUX(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(1)), 0x7, 24); +CLOCK_COM_DIV(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(1)), 0, 16); +CLOCK_COM_GATE(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(1)), 31); +/* spdifin */ +CLOCK_COM_MUX(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 0x7, 24); +CLOCK_COM_DIV(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 0, 8); +CLOCK_COM_GATE(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 31); +/* spdifout */ +CLOCK_COM_MUX(spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_CTRL), 0x7, 24); +CLOCK_COM_DIV(spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_CTRL), 0, 10); +CLOCK_COM_GATE(spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_CTRL), 31); +/* audio resample_a */ +CLOCK_COM_MUX(resample_a, + AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 0xf, 24); +CLOCK_COM_DIV(resample_a, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 0, 8); +CLOCK_COM_GATE(resample_a, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 31); +/* audio locker_out */ +CLOCK_COM_MUX(locker_out, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 0xf, 24); +CLOCK_COM_DIV(locker_out, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 16, 8); +CLOCK_COM_GATE(locker_out, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 31); +/* audio locker_in */ +CLOCK_COM_MUX(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 0xf, 8); +CLOCK_COM_DIV(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 0, 8); +CLOCK_COM_GATE(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 15); +/* pdmin0 */ +CLOCK_COM_MUX(pdmin0, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL0), 0x7, 24); +CLOCK_COM_DIV(pdmin0, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL0), 0, 16); +CLOCK_COM_GATE(pdmin0, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL0), 31); +/* pdmin1 */ +CLOCK_COM_MUX(pdmin1, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL1), 0x7, 24); +CLOCK_COM_DIV(pdmin1, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL1), 0, 16); +CLOCK_COM_GATE(pdmin1, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL1), 31); +/* spdifout b*/ +CLOCK_COM_MUX(spdifout_b, + AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_B_CTRL), 0x7, 24); +CLOCK_COM_DIV(spdifout_b, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_B_CTRL), 0, 10); +CLOCK_COM_GATE(spdifout_b, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_B_CTRL), 31); +/* audio resample_b */ +CLOCK_COM_MUX(resample_b, + AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEB_CTRL), 0xf, 24); +CLOCK_COM_DIV(resample_b, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEB_CTRL), 0, 8); +CLOCK_COM_GATE(resample_b, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEB_CTRL), 31); +/* spdifin_lb, div is a fake */ +CLOCK_COM_MUX(spdifin_lb, + AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_B_CTRL), 0x1, 30); +CLOCK_COM_DIV(spdifin_lb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_B_CTRL), 0, 29); +CLOCK_COM_GATE(spdifin_lb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_B_CTRL), 31); +/* audio eqdrc */ +CLOCK_COM_MUX(eqdrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_EQDRC_CTRL0), 0x7, 24); +CLOCK_COM_DIV(eqdrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_EQDRC_CTRL0), 0, 16); +CLOCK_COM_GATE(eqdrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_EQDRC_CTRL0), 31); +/* audio vad */ +CLOCK_COM_MUX(vad, AUD_ADDR_OFFSET(EE_AUDIO_VAD_CLK_CTRL), 0x7, 24); +CLOCK_COM_DIV(vad, AUD_ADDR_OFFSET(EE_AUDIO_VAD_CLK_CTRL), 0, 16); +CLOCK_COM_GATE(vad, AUD_ADDR_OFFSET(EE_AUDIO_VAD_CLK_CTRL), 31); +/* EARC TX CMDC */ +CLOCK_COM_MUX(earctx_cmdc, + AUD_ADDR_OFFSET(EE_AUDIO_EARCTX_CMDC_CLK_CTRL), 0x7, 24); +CLOCK_COM_DIV(earctx_cmdc, + AUD_ADDR_OFFSET(EE_AUDIO_EARCTX_CMDC_CLK_CTRL), 0, 16); +CLOCK_COM_GATE(earctx_cmdc, + AUD_ADDR_OFFSET(EE_AUDIO_EARCTX_CMDC_CLK_CTRL), 31); +/* EARC TX DMAC */ +CLOCK_COM_MUX(earctx_dmac, + AUD_ADDR_OFFSET(EE_AUDIO_EARCTX_DMAC_CLK_CTRL), 0x7, 24); +CLOCK_COM_DIV(earctx_dmac, + AUD_ADDR_OFFSET(EE_AUDIO_EARCTX_DMAC_CLK_CTRL), 0, 16); +CLOCK_COM_GATE(earctx_dmac, + AUD_ADDR_OFFSET(EE_AUDIO_EARCTX_DMAC_CLK_CTRL), 31); +/* EARC RX CMDC */ +CLOCK_COM_MUX(earcrx_cmdc, + AUD_ADDR_OFFSET(EE_AUDIO_EARCRX_CMDC_CLK_CTRL), 0x7, 24); +CLOCK_COM_DIV(earcrx_cmdc, + AUD_ADDR_OFFSET(EE_AUDIO_EARCRX_CMDC_CLK_CTRL), 0, 16); +CLOCK_COM_GATE(earcrx_cmdc, + AUD_ADDR_OFFSET(EE_AUDIO_EARCRX_CMDC_CLK_CTRL), 31); +/* EARC RX DMAC */ +CLOCK_COM_MUX(earcrx_dmac, + AUD_ADDR_OFFSET(EE_AUDIO_EARCRX_DMAC_CLK_CTRL), 0x7, 24); +CLOCK_COM_DIV(earcrx_dmac, + AUD_ADDR_OFFSET(EE_AUDIO_EARCRX_DMAC_CLK_CTRL), 0, 16); +CLOCK_COM_GATE(earcrx_dmac, + AUD_ADDR_OFFSET(EE_AUDIO_EARCRX_DMAC_CLK_CTRL), 31); + +static int tm2_clks_init(struct clk **clks, void __iomem *iobase) +{ + IOMAP_COM_CLK(mclk_a, iobase); + clks[CLKID_AUDIO_MCLK_A] = REGISTER_CLK_COM(mclk_a); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_A])); + + IOMAP_COM_CLK(mclk_b, iobase); + clks[CLKID_AUDIO_MCLK_B] = REGISTER_CLK_COM(mclk_b); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_B])); + + IOMAP_COM_CLK(mclk_c, iobase); + clks[CLKID_AUDIO_MCLK_C] = REGISTER_CLK_COM(mclk_c); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_C])); + + IOMAP_COM_CLK(mclk_d, iobase); + clks[CLKID_AUDIO_MCLK_D] = REGISTER_CLK_COM(mclk_d); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_D])); + + IOMAP_COM_CLK(mclk_e, iobase); + clks[CLKID_AUDIO_MCLK_E] = REGISTER_CLK_COM(mclk_e); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_E])); + + IOMAP_COM_CLK(mclk_f, iobase); + clks[CLKID_AUDIO_MCLK_F] = REGISTER_CLK_COM(mclk_f); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_F])); + + IOMAP_COM_CLK(spdifin, iobase); + clks[CLKID_AUDIO_SPDIFIN] = REGISTER_CLK_COM(spdifin); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_SPDIFIN])); + + IOMAP_COM_CLK(spdifout, iobase); + clks[CLKID_AUDIO_SPDIFOUT_A] = REGISTER_CLK_COM(spdifout); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_SPDIFOUT_A])); + + IOMAP_COM_CLK(resample_a, iobase); + clks[CLKID_AUDIO_RESAMPLE_A] = REGISTER_AUDIOCLK_COM(resample_a); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_RESAMPLE_A])); + + IOMAP_COM_CLK(locker_out, iobase); + clks[CLKID_AUDIO_LOCKER_OUT] = REGISTER_AUDIOCLK_COM(locker_out); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_LOCKER_OUT])); + + IOMAP_COM_CLK(locker_in, iobase); + clks[CLKID_AUDIO_LOCKER_IN] = REGISTER_AUDIOCLK_COM(locker_in); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_LOCKER_IN])); + + IOMAP_COM_CLK(pdmin0, iobase); + clks[CLKID_AUDIO_PDMIN0] = REGISTER_CLK_COM(pdmin0); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_PDMIN0])); + + IOMAP_COM_CLK(pdmin1, iobase); + clks[CLKID_AUDIO_PDMIN1] = REGISTER_CLK_COM(pdmin1); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_PDMIN1])); + + IOMAP_COM_CLK(spdifout_b, iobase); + clks[CLKID_AUDIO_SPDIFOUT_B] = REGISTER_CLK_COM(spdifout_b); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_SPDIFOUT_B])); + + IOMAP_COM_CLK(resample_b, iobase); + clks[CLKID_AUDIO_RESAMPLE_B] = REGISTER_AUDIOCLK_COM(resample_b); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_RESAMPLE_B])); + + IOMAP_COM_CLK(spdifin_lb, iobase); + clks[CLKID_AUDIO_SPDIFIN_LB] = REGISTER_CLK_COM(spdifin_lb); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_SPDIFIN_LB])); + + IOMAP_COM_CLK(eqdrc, iobase); + clks[CLKID_AUDIO_EQDRC] = REGISTER_CLK_COM(eqdrc); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_EQDRC])); + + IOMAP_COM_CLK(vad, iobase); + clks[CLKID_AUDIO_VAD] = REGISTER_CLK_COM(vad); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_VAD])); + + IOMAP_COM_CLK(earctx_cmdc, iobase); + clks[CLKID_EARCTX_CMDC] = REGISTER_CLK_COM(earctx_cmdc); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_EARCTX_CMDC])); + + IOMAP_COM_CLK(earctx_dmac, iobase); + clks[CLKID_EARCTX_DMAC] = REGISTER_CLK_COM(earctx_dmac); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_EARCTX_DMAC])); + + IOMAP_COM_CLK(earcrx_cmdc, iobase); + clks[CLKID_EARCRX_CMDC] = REGISTER_CLK_COM(earcrx_cmdc); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_EARCRX_CMDC])); + + IOMAP_COM_CLK(earcrx_dmac, iobase); + clks[CLKID_EARCRX_DMAC] = REGISTER_CLK_COM(earcrx_dmac); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_EARCRX_DMAC])); + + return 0; +} + +struct audio_clk_init tm2_audio_clks_init = { + .clk_num = NUM_AUDIO_CLKS, + .clk_gates = tm2_clk_gates_init, + .clks = tm2_clks_init, +};