From 30f84d3755f43f8083017252a942d7cbac4bb973 Mon Sep 17 00:00:00 2001 From: Yifeng Zhao Date: Thu, 17 Jun 2021 11:13:21 +0800 Subject: [PATCH] mmc: sdhci-of-dwcmshc: rk3568: do not enable DLL while the clock rate less than 52mhz The DLL may not be able to lock while the clock rate less than 52mhz. Signed-off-by: Yifeng Zhao Change-Id: Ifacc3da516d78f5f242d8b03a60500a7dfe28993 --- drivers/mmc/host/sdhci-of-dwcmshc.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index 798a7591b93d..f344bd300018 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -163,10 +163,6 @@ static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock) host->mmc->actual_clock = 0; - /* DO NOT TOUCH THIS SETTING */ - extra = DWCMSHC_EMMC_DLL_DLYENA | - DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; - sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); if (clock == 0) return; @@ -186,9 +182,11 @@ static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock) extra &= ~BIT(0); sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3); - if (clock <= 400000) { - /* Disable DLL to reset sample clock */ + if (clock <= 52000000) { + /* Disable DLL and reset both of sample and drive clock */ sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK); + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); return; } @@ -197,6 +195,15 @@ static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock) udelay(1); sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL); + /* + * We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but + * we must set it in higher speed mode. + */ + extra = DWCMSHC_EMMC_DLL_DLYENA | + DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; + + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); + /* Init DLL settings */ extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT | 0x2 << DWCMSHC_EMMC_DLL_INC |