From 30ffe9accda08d02299626ca64b75c96e1c2f9bd Mon Sep 17 00:00:00 2001
From: David Wu <david.wu@rock-chips.com>
Date: Tue, 3 Dec 2019 11:40:46 +0800
Subject: [PATCH] arm64: dts: rockchip: Fix otg function for rk3368 sheep

Enable otg to apply dwc2-controller and u2phy_otg driver.

Change-Id: I5d5b7623ff18b1bf14f8b6e91620bfb88770cd63
Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 .../boot/dts/rockchip/rk3368-android.dtsi     | 46 -------------------
 arch/arm64/boot/dts/rockchip/rk3368-sheep.dts | 20 ++++++++
 2 files changed, 20 insertions(+), 46 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi
index fcb158374611..74be9cff5fca 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi
@@ -111,42 +111,6 @@
 		dma-coherent;
 		status = "okay";
 	};
-
-	dwc_control_usb: dwc-control-usb {
-		compatible = "rockchip,rk3368-dwc-control-usb";
-		status = "okay";
-
-		rockchip,grf = <&grf>;
-		grf-offset = <0x04bc>; /* GRF_SOC_STATUS for USB2.0 OTG */
-		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "otg_id", "otg_bvalid",
-				  "otg_linestate", "host0_linestate";
-		clocks = <&cru HCLK_USB_PERI>;
-		clock-names = "hclk_usb_peri";
-
-		otg_drv_gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
-		rockchip,remote_wakeup;
-		rockchip,usb_irq_wakeup;
-
-		usb_bc {
-			compatible = "inno,phy";
-			regbase = &dwc_control_usb;
-			rk_usb,bvalid     = <0x4bc 23 1>;
-			rk_usb,iddig      = <0x4bc 26 1>;
-			rk_usb,vdmsrcen   = <0x718 12 1>;
-			rk_usb,vdpsrcen   = <0x718 11 1>;
-			rk_usb,rdmpden    = <0x718 10 1>;
-			rk_usb,idpsrcen   = <0x718  9 1>;
-			rk_usb,idmsinken  = <0x718  8 1>;
-			rk_usb,idpsinken  = <0x718  7 1>;
-			rk_usb,dpattach   = <0x4b8 31 1>;
-			rk_usb,cpdet      = <0x4b8 30 1>;
-			rk_usb,dcpattach  = <0x4b8 29 1>;
-		};
-	};
 };
 
 &cluster1_opp {
@@ -268,16 +232,6 @@
 
 &usb_otg {
 	status = "okay";
-
-	compatible = "rockchip,rk3368-usb";
-	clocks = <&cru SCLK_OTGPHY0>, <&cru HCLK_OTG0>;
-	clock-names = "sclk_otgphy0", "otg";
-	resets = <&cru SRST_USBOTG_AHB>,
-		 <&cru SRST_USBOTG_PHY>,
-		 <&cru SRST_USBOTG_CON>;
-	reset-names = "otg_ahb", "otg_phy", "otg_controller";
-	/* 0 - Normal, 1 - Force Host, 2 - Force Device */
-	rockchip,usb-mode = <0>;
 };
 
 &pinctrl {
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-sheep.dts b/arch/arm64/boot/dts/rockchip/rk3368-sheep.dts
index 79cf6a49d76c..16db52eddd96 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-sheep.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-sheep.dts
@@ -179,6 +179,17 @@
 		regulator-always-on;
 	};
 
+	vcc_otg_vbus: otg-vbus-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&otg_vbus_drv>;
+		regulator-name = "vcc_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+	};
+
 	xin32k: xin32k {
 		compatible = "fixed-clock";
 		clock-frequency = <32768>;
@@ -608,6 +619,11 @@
 		phy-supply = <&vcc_host>;
 		status = "okay";
 	};
+
+	u2phy_otg: otg-port {
+		vbus-supply = <&vcc_otg_vbus>;
+		status = "okay";
+	};
 };
 
 &usb_host0_ehci {
@@ -696,5 +712,9 @@
 		host_vbus_drv: host-vbus-drv {
 			rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		otg_vbus_drv: otg-bus-drv {
+			rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
 	};
 };