From 319229602927ef34c6d3bca9a85bb8d7d324d9ce Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Tue, 1 Jul 2025 17:34:42 +0800 Subject: [PATCH] pwm: rockchip: Add comments for why to add delay before disabling the dclk for PWM v4 Fixes: 42e759004f12 ("pwm: rockchip: add one period delay before disabling the dclk") Change-Id: I612fde2adf60940e17146a115a104caf302109b2 Signed-off-by: Damon Ding --- drivers/pwm/pwm-rockchip.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c index 0037c4046efa..5c4c5669eec5 100644 --- a/drivers/pwm/pwm-rockchip.c +++ b/drivers/pwm/pwm-rockchip.c @@ -873,6 +873,11 @@ static int rockchip_pwm_enable_v4(struct pwm_chip *chip, struct pwm_device *pwm, writel_relaxed(PWM_EN(enable) | PWM_CLK_EN(enable), pc->base + ENABLE); + /* + * For pwm v4, the disable operation, which sets polarity to inactive state, + * will not take effect until the end of current period. Therefore, it makes + * sense to delay one period before disabling the dclk. + */ if (!enable) { pwm_get_state(pwm, &curstate); delay_us = DIV_ROUND_UP_ULL(curstate.period, NSEC_PER_USEC);