diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 08c8d50e230b..c4f2c4f7717d 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -1067,6 +1067,15 @@ static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode)
 		udphy->mode_change = false;
 		udphy->status = UDPHY_MODE_NONE;
 
+		/*
+		 * For DP 4xlanes + USB2 only scenario, it needs to
+		 * select utmi clock from the USB2 PHY for the USB
+		 * controller source clock, then it can safely disable
+		 * the USBDP PHY later to reconfigure lanes for DP.
+		 */
+		if (udphy->mode == UDPHY_MODE_DP)
+			udphy_u3_port_disable(udphy, true);
+
 		ret = udphy_disable(udphy);
 		if (ret)
 			return ret;