From 31bf36387a4a0fcaa409bbdc64683d9a0134b88f Mon Sep 17 00:00:00 2001 From: William Wu Date: Wed, 8 May 2024 16:37:40 +0800 Subject: [PATCH] phy: rockchip: usbdp: Select utmi clock for DP 4lanes mode For Type-C to DP 4xlanes adapter, it is detected as DP 2xlanes + USB3.0 DFP at the first time, and after VDM negotiation completed, it can be detected as DP 4xlanes, in this case, the USBDP PHY needs to do mode change in the udphy_power_on. During the mode change process, the USBDP PHY will disable the PHY clocks and assert the PHY reset, this also turn off the PIPE clock which used for the source clock of the USB controller. In order to safely disable the USBDP PHY, it needs to select the UTMI clock instead of the PIPE clock for the USB controller. Fixes: 0b1d72b40cc4 ("phy: rockchip: usbdp: Avoid access usb grf during dp phy power on") Signed-off-by: William Wu Change-Id: I5e055aa466af936a9a7fd1a59bbbe4ac8350a696 --- drivers/phy/rockchip/phy-rockchip-usbdp.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c index 08c8d50e230b..c4f2c4f7717d 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -1067,6 +1067,15 @@ static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode) udphy->mode_change = false; udphy->status = UDPHY_MODE_NONE; + /* + * For DP 4xlanes + USB2 only scenario, it needs to + * select utmi clock from the USB2 PHY for the USB + * controller source clock, then it can safely disable + * the USBDP PHY later to reconfigure lanes for DP. + */ + if (udphy->mode == UDPHY_MODE_DP) + udphy_u3_port_disable(udphy, true); + ret = udphy_disable(udphy); if (ret) return ret;